1. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 x86 Assembler

2. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Disclaimer I am not an x86 assembler expert. I have never written an x86 assembler program. (I am proficient in IBM S/360 Assembler and LC3 Assembler.) You will NOT be expected to WRITE x86 assembler. You WILL be expected to be able to READ x86 assembler!

3. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Instruction Set Architecture (ISA) Contract between Hardware Designer and Programmer Which parts of the hardware the programmer is allowed to see and use Many machines may have the same architecture E.g. x86 supported by Intel, AMD, HP, Sun, IBM, Motorola, … A single machine sometimes supports multiple architectures E.g. x86 / x86-64 Usually for downward compatability

4. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 The architecture compatibility dilemma Over time, things evolve : hardware, software, new uses Customers hate architectural changes Lose investment in software Architecture changes introduce new bugs Customers love the latest new feature Can’t wait for googleplex address space, … Resolution: Architecture Supersets

5. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Intel Milestones DateChipData WidthTransistorsClock RateUsage 1972800883.5K0.8 MHzMonitors, Controllers 197480808 (some 16)6K2 MHz+ Calculators 197880861629K10 MHzIBM PC/DOS – First x86 19858038632275K40 MHzWindows+Linux 1993Pentium P5323.1M66 MHzditto 2004Pentium 4F64125M3.8 GHzditto 2008Core i764731M3.33 GHzditto 2014Core i7 extreme641.4B3.5 GHzditto

6. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 37 Years of Evolution X86-64 / EM64t X86-32/IA32 X86-16 8086 286 386 486 Pentium Pentium MMX Pentium III Pentium 4 Pentium 4E Pentium 4F Core 2 Duo Core i7 ArchitecturesProcessors MMX SSE SSE2 SSE3 SSE4

7. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 x86 Clones: Advanced Micro Devices Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits

8. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 CPU Assembly Programmer’s View of x86 Memory Byte addressable array Code, user data, (some) OS data Includes stack used to support procedures Programmer-Visible State PC: Program counter Address of next instruction Called “EIP” (IA32) or “RIP” (x86-64) Register file Heavily used program data Condition codes Store status information about most recent arithmetic operation Used for conditional branching Arithmetic/Logic Unit (ALU) Performs Instructions PC Registers Memory Object Code Program Data OS Data Addresses Data Instructions Stack Condition Codes ALU

9. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 x86 Generalizations Designed to be Compiler Friendly Stack manipulation instructions ALU uses data from memory as well as registers! Downward Compatible Newer versions are supersets of older versions CISC (Complex Instruction Set Computing)

10. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 CISC Concept IMULT X,Y Micro-code … IMULT -> SHIFTL 1,X ADD ACCUM,Y SHIFTL 1, X … ADD ACCUM,Y

11. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 RISC Concept ADD ACCUM,Y

12. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Origin Accumulate Counter Data Base Source Index Destination Index Stack Pointer base Pointer x86 Integer Registers %rdi %rax %rcx %rdx %rsi %rbx %rbp %rsp %eax %ecx %edx %ebx %esi %edi %esp %ebp %ax %cx %dx %bx %si %di %sp %bp %ah%al%ch%cl%dh%dl%bh%bl 8 16 32 64

13. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 x86 Data “Types” No type checking - Instruction and/or context implies data type Arithmetic instructions treat operands as numbers Either signed or unsigned! Instruction suffix used to identify precision of arguments b – 1 byte (8 bits) w – word (2 bytes, 16 bits) l – long word (4 bytes, 32 bits) q – quad word (8 bytes, 64 bits) With no suffix, register type implies precision of arguments ah/al – b – 8 bits ax – w – 16 bits eax – l – 32 bits rax – q – 64 bits Floating point – 4, 8, or 10 bytes

14. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 x86 Assembler Syntax [ :] arg1[,arg2…] [; comment] Label optional – identifies start of this line mnemonic – See http://ref.x86asm.net/ for a complete listhttp://ref.x86asm.net/ Up to 4 arguments Comment ends at the end of this line

15. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Assembler Argument Generalities Direction: LEFT to RIGHT ⇒ (AT&T syntax… INTEL syntax is RtoL) mov 5,eax; eax=5 (move 5 into register eax) add bx, ax ; ax = ax + bx or ax+=bx (add bx to ax and store in ax) Optional argument prefixes % - register e.g. “movl 5,%eax” $ - immediate value e.g. “movl $5,%eax” Arguments may be: register, immediate value, memory reference One (but not both) argument may be a memory reference! at least one argument must be a register or immediate value

16. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Immediate (literal) values Similar to C Conventions…. Numbers are decimal by default, octal if preceded by 0, hex if preceded by 0x Single characters are enclosed in single quotes, including special characters such as ‘\n’, ‘\t’ Strings are arrays of characters enclosed in double quotes

17. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Basic x86 addressing modes Normal: Register contains address of target in memory Parenthesis indicate “Use Value at this address” movl (%ecx),%eax ; Put the value at memory[ecx] into eax Displacement: Register is near address of target in memory Offset from register specified before parenthesis movl 8(%ebp),%edx ; Put the value at 8 past the base pointer into edx See http://en.wikipedia.org/wiki/X86#Addressing_modes if you need the entire story – but it’s complicatedhttp://en.wikipedia.org/wiki/X86#Addressing_modes

18. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 The MOV instruction Most often used instruction! More “copy” than “move” Copies 1,2,4, or 8 bytes from ARG1 to ARG2 mov $-12,%eax ; put -12 into 4 byte eax register mov $0xffff,(%esp) ; put -1 at top of stack mov 12(%ebp),%eax ; copy data at 12 past base pointer into eax

19. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Logic Instructions Standard 2 arg: and or xor shl shr and %ebx,%eax ; eax=eax & ebx shr $4,%eax; eax = (unsigned)eax>>4 Single argument: not neg not %eax ; flip bits in eax neg %ebx; take two’s complement (flip bits and add 1) of ebx

20. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Arithmetic Instructions Standard integer arithmetic: add sub add $10,(%eax); (*eax)=(*eax)+10 sub $4,%esp ; esp=esp-4 (move stack pointer down) “Special” integer arithmetic: imul idiv imul cannot write to memory idiv divides register pair (EDX:EAX) and puts quotient/remainder back Single argument: inc dec inc %eax; eax=eax+1 – same as add eax,1 dec (%esp) ; decrement the value at the top of the stack by 1 Floating Point Instructions

21. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Dealing with Pointers Load effective address: lea Used for implicit arrays/structures, etc. lea (array),%eax mov $0,%edx loop: add (%eax),%edx add $4,%eax cmp endarray,%eax jle loop mov %eax,(sum)

22. Binghamton University CS-220 Spring 2015 Binghamton University CS-220 Spring 2015 Not done yet… Next – x86 control instructions…