1. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 1 - 160mm boards, crate on the front of the rack + no major changes in layout (minimum risk, no additional work) + low cost - inserting cables to the back of the crate may be impossible - cables obstruct the air flow (support system for FEB cables needed)

2. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 2 - 160mm boards, crate on the back of the rack + no major changes in layout (minimum risk, no additional work) + low cost + FEB cables easily accessible - boards are hidden (LED:s not visible, boards&frontplane hard to insert/remove) - cover plate needed for the front - cables are difficult to insert/remove from the front - air-flow control needed (otherwise no air will go through the crate)

3. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 3 - 500mm boards, crate on the front of the rack + front and back of the boards easy to access + no additional mechanical design needed + good air-flow - expensive (we are buing empty circuit board area) - risky (long tracks create timing uncertanties, long flexible board is not easy to produce, possible reliability problems from flexible board)

4. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 3A – present link board design extended to 500mm + no major changes needed - there is a risk this does not work (performance degradation propable) - extra work in circuit board design (300mm traces need careful design work) LVDS buffers Xilinx 2 Xilinx 1 FEB cables 300mm traces

5. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 3B – boards extended to 500mm, front bus moved to the back + less risk than in 3A - extra work (redesign of the backplane) - ~50mm more space needed (is this even possible?) - more expensive that 3A (more circuit board area) LVDS buffers Xilinx 2 Xilinx 1 FEB cables

6. Matti Iskanius 31.05.2005 Link system board size scenarios Scenario 3C – boards extended to 500mm, redesign of the frontbus (Frontbus is redesigned as 9 serial poin-to-point links from the CB) + less risk than in 3A - major desing work LVDS buffers Xilinx 2 Xilinx 1 FEB cables