1. Average Gate-width (W Avg ) computation Diffusion boundary may not be straight  match diffusion area in dotted rectangle (a, b > misalignment tolerance) Average width = separation b/w computed diffusion boundaries Average Gate-length (L Avg ) computation Take intersection b/w diffusion and poly  get gate Gate not rectangular  rectilinearize (midpoint-sum approx.) L Avg computed from gate-lengths of slices after rectilinearization Specific to analysis objective. Two modes: Expression mode: computed using analytical expressionsExpression mode: computed using analytical expressions e.g., for delay objective: L Avg = W Avg /Σ i (W i /L i ) for capacitance objective: L Avg = Σ i (W i L i )/W Avg for capacitance objective: L Avg = Σ i (W i L i )/W Avg Lookup-table mode: computed using table of device on- and off- currents for different gate-lengths and gate-widthsLookup-table mode: computed using table of device on- and off- currents for different gate-lengths and gate-widths Mapping to a cell in library Each cell instance prints different  uniquification of each instance  need to reconstruct hierarchy Equivalent gate-length (L Eq ) computation: derived from L Avg ’s of devices in the cell. Specific to analysis objective. L Eq for objective: setup is max. of L Avg ’s.setup is max. of L Avg ’s. hold is min. of L Avg ’s.hold is min. of L Avg ’s. capacitance is computed to match the gate areacapacitance is computed to match the gate area leakage is computed to match the total leakage  can consider stacking effect to weigh devices differentlyleakage is computed to match the total leakage  can consider stacking effect to weigh devices differently For each cell, variant from library selected that has closest gate-length to L Eq of cell, and master updated in output Verilog Average Gate-width (W Avg ) computation Diffusion boundary may not be straight  match diffusion area in dotted rectangle (a, b > misalignment tolerance) Average width = separation b/w computed diffusion boundaries Average Gate-length (L Avg ) computation Take intersection b/w diffusion and poly  get gate Gate not rectangular  rectilinearize (midpoint-sum approx.) L Avg computed from gate-lengths of slices after rectilinearization Specific to analysis objective. Two modes: Expression mode: computed using analytical expressionsExpression mode: computed using analytical expressions e.g., for delay objective: L Avg = W Avg /Σ i (W i /L i ) for capacitance objective: L Avg = Σ i (W i L i )/W Avg for capacitance objective: L Avg = Σ i (W i L i )/W Avg Lookup-table mode: computed using table of device on- and off- currents for different gate-lengths and gate-widthsLookup-table mode: computed using table of device on- and off- currents for different gate-lengths and gate-widths Mapping to a cell in library Each cell instance prints different  uniquification of each instance  need to reconstruct hierarchy Equivalent gate-length (L Eq ) computation: derived from L Avg ’s of devices in the cell. Specific to analysis objective. L Eq for objective: setup is max. of L Avg ’s.setup is max. of L Avg ’s. hold is min. of L Avg ’s.hold is min. of L Avg ’s. capacitance is computed to match the gate areacapacitance is computed to match the gate area leakage is computed to match the total leakage  can consider stacking effect to weigh devices differentlyleakage is computed to match the total leakage  can consider stacking effect to weigh devices differently For each cell, variant from library selected that has closest gate-length to L Eq of cell, and master updated in output Verilog Inputs: Litho-simulated GDSLitho-simulated GDS Drawn layout: to correlate GDS with designDrawn layout: to correlate GDS with design Std. cell GDS and SPICE netlists: to run LVS  find location of each device in a cell layoutStd. cell GDS and SPICE netlists: to run LVS  find location of each device in a cell layout Std. cell library w/ gate-length changed for devices in cellsStd. cell library w/ gate-length changed for devices in cells Objective: type of analysis to be performed e.g., setup time, hold time, leakage, dynamic powerObjective: type of analysis to be performed e.g., setup time, hold time, leakage, dynamic powerOutputs: Objective-specific Verilog: Verilog with cell masters modified to better estimate on-silicon power/performanceObjective-specific Verilog: Verilog with cell masters modified to better estimate on-silicon power/performance SPEF: modified parasiticsSPEF: modified parasitics Device Analyses: For each cell, analyzes litho-simulated poly layer to estimate gate-length of cell’s devices  searches library for similar cell with non-nominal gate-lengths (cell variant)  modifies master in Verilog Interconnect Analyses: For each interconnect, analyzes impact of non-ideal geometry on parasitics  updates SPEF Inputs: Litho-simulated GDSLitho-simulated GDS Drawn layout: to correlate GDS with designDrawn layout: to correlate GDS with design Std. cell GDS and SPICE netlists: to run LVS  find location of each device in a cell layoutStd. cell GDS and SPICE netlists: to run LVS  find location of each device in a cell layout Std. cell library w/ gate-length changed for devices in cellsStd. cell library w/ gate-length changed for devices in cells Objective: type of analysis to be performed e.g., setup time, hold time, leakage, dynamic powerObjective: type of analysis to be performed e.g., setup time, hold time, leakage, dynamic powerOutputs: Objective-specific Verilog: Verilog with cell masters modified to better estimate on-silicon power/performanceObjective-specific Verilog: Verilog with cell masters modified to better estimate on-silicon power/performance SPEF: modified parasiticsSPEF: modified parasitics Device Analyses: For each cell, analyzes litho-simulated poly layer to estimate gate-length of cell’s devices  searches library for similar cell with non-nominal gate-lengths (cell variant)  modifies master in Verilog Interconnect Analyses: For each interconnect, analyzes impact of non-ideal geometry on parasitics  updates SPEF Lithography simulation not connected to design  we proposed a novel flow to link lithography simulation w/ off-the-shelf analyses toolsLithography simulation not connected to design  we proposed a novel flow to link lithography simulation w/ off-the-shelf analyses tools For device analyses, device rectilinearized and L Avg computed. Devices in each cell considered to find L Eq of cell and closest library variant usedFor device analyses, device rectilinearized and L Avg computed. Devices in each cell considered to find L Eq of cell and closest library variant used For interconnect analyses, impact of change in dimension on capacitance and resistance estimated using field-solver for template configurations and SPEF database modifiedFor interconnect analyses, impact of change in dimension on capacitance and resistance estimated using field-solver for template configurations and SPEF database modified Lithography simulation-based analyses more accurate and adequately fastLithography simulation-based analyses more accurate and adequately fast Ongoing work:Ongoing work: Consider impact of slice location on L Avg computationConsider impact of slice location on L Avg computation Transistor-level delay and power modeling to replace or supplement library chacterizationTransistor-level delay and power modeling to replace or supplement library chacterization Improve speed and accuracy of interconnect analysesImprove speed and accuracy of interconnect analyses Lithography simulation not connected to design  we proposed a novel flow to link lithography simulation w/ off-the-shelf analyses toolsLithography simulation not connected to design  we proposed a novel flow to link lithography simulation w/ off-the-shelf analyses tools For device analyses, device rectilinearized and L Avg computed. Devices in each cell considered to find L Eq of cell and closest library variant usedFor device analyses, device rectilinearized and L Avg computed. Devices in each cell considered to find L Eq of cell and closest library variant used For interconnect analyses, impact of change in dimension on capacitance and resistance estimated using field-solver for template configurations and SPEF database modifiedFor interconnect analyses, impact of change in dimension on capacitance and resistance estimated using field-solver for template configurations and SPEF database modified Lithography simulation-based analyses more accurate and adequately fastLithography simulation-based analyses more accurate and adequately fast Ongoing work:Ongoing work: Consider impact of slice location on L Avg computationConsider impact of slice location on L Avg computation Transistor-level delay and power modeling to replace or supplement library chacterizationTransistor-level delay and power modeling to replace or supplement library chacterization Improve speed and accuracy of interconnect analysesImprove speed and accuracy of interconnect analyses Lithography Simulation-Based Full-Chip Design Analyses Presenter: Puneet Sharma (sharma@ucsd.edu) P. Gupta †, A. B. Kahng †‡, S. Nakagawa †, S. Shah Ψ, P. Sharma ‡ † Blaze DFM Inc., Sunnyvale, CA ‡ ECE Department, U.C. San Diego Ψ EECS Department, U. of Michigan Timing and power sign-off before RETTiming and power sign-off before RET Similarity b/w drawn and printed design poor due to RETs and process variationsSimilarity b/w drawn and printed design poor due to RETs and process variations  Large difference b/w signed-off and on-silicon power & delay Lithography simulation predicts on-silicon geometries at different process cornersLithography simulation predicts on-silicon geometries at different process corners However, lithography simulation purely geometry-based and not connected to design in any wayHowever, lithography simulation purely geometry-based and not connected to design in any way We use lithography simulation w/ off-the-shelf design analysis tools to predict on-silicon performance & powerWe use lithography simulation w/ off-the-shelf design analysis tools to predict on-silicon performance & power  Facilitates more accurate estimation  lesser guardbanding Previous work: Yang et al. DAC 05 – similar flow suggested; several non-trivial details lacking; timing analysis only (for critical paths); no interconnects consideredPrevious work: Yang et al. DAC 05 – similar flow suggested; several non-trivial details lacking; timing analysis only (for critical paths); no interconnects considered Timing and power sign-off before RETTiming and power sign-off before RET Similarity b/w drawn and printed design poor due to RETs and process variationsSimilarity b/w drawn and printed design poor due to RETs and process variations  Large difference b/w signed-off and on-silicon power & delay Lithography simulation predicts on-silicon geometries at different process cornersLithography simulation predicts on-silicon geometries at different process corners However, lithography simulation purely geometry-based and not connected to design in any wayHowever, lithography simulation purely geometry-based and not connected to design in any way We use lithography simulation w/ off-the-shelf design analysis tools to predict on-silicon performance & powerWe use lithography simulation w/ off-the-shelf design analysis tools to predict on-silicon performance & power  Facilitates more accurate estimation  lesser guardbanding Previous work: Yang et al. DAC 05 – similar flow suggested; several non-trivial details lacking; timing analysis only (for critical paths); no interconnects consideredPrevious work: Yang et al. DAC 05 – similar flow suggested; several non-trivial details lacking; timing analysis only (for critical paths); no interconnects considered Invokes device analyses per instance and interconnect analyses for SPEF database Can perform caching and distributed processing Mixed-mode objective Separate Verilogs generated for different objectives  difficult to manage and non-standard  mixed-mode objective generates one Verilog accurate for all objectives as follows: Step 1: hold objective for hold-critical cellsStep 1: hold objective for hold-critical cells Step 2: setup objective for setup-critical cellsStep 2: setup objective for setup-critical cells Step 3: capacitance objective for fanout cells of hold and setup critical cells not assigned objectiveStep 3: capacitance objective for fanout cells of hold and setup critical cells not assigned objective Step 4: leakage/dynamic power for all other cellsStep 4: leakage/dynamic power for all other cells Invokes device analyses per instance and interconnect analyses for SPEF database Can perform caching and distributed processing Mixed-mode objective Separate Verilogs generated for different objectives  difficult to manage and non-standard  mixed-mode objective generates one Verilog accurate for all objectives as follows: Step 1: hold objective for hold-critical cellsStep 1: hold objective for hold-critical cells Step 2: setup objective for setup-critical cellsStep 2: setup objective for setup-critical cells Step 3: capacitance objective for fanout cells of hold and setup critical cells not assigned objectiveStep 3: capacitance objective for fanout cells of hold and setup critical cells not assigned objective Step 4: leakage/dynamic power for all other cellsStep 4: leakage/dynamic power for all other cells Layout of a small circuit litho-simulated at 0nm and 200nm defocus Analyses for setup and leakage objectives; color annotations show L Eq Practical runtime: 70K cell design in 1hr Layout of a small circuit litho-simulated at 0nm and 200nm defocus Analyses for setup and leakage objectives; color annotations show L Eq Practical runtime: 70K cell design in 1hr Parasitic-change lookup table: predicts change in capacitance and resistance given change in interconnect width and spacing Parameters: width, width and spacing of right and left neighbors, layer, densities of above and below layers Table created by field-solver simulations for geometries generated for a technology Lithography simulation-based parasitic extraction SPEF segment to routing segment mapping: for each routing segment in SPEF, corresponding geometries in drawn and litho-simulated layouts are found using SPEF node coordinates Shape rectilinearization: litho-simulated routing segments not rectilinear  perform rectilinearization similar to gate-poly SPEF database modification: parasitic change computed from lookup table for each slice (from rectilinearization)  parasitic network reduction  update SPEF database Parasitic-change lookup table: predicts change in capacitance and resistance given change in interconnect width and spacing Parameters: width, width and spacing of right and left neighbors, layer, densities of above and below layers Table created by field-solver simulations for geometries generated for a technology Lithography simulation-based parasitic extraction SPEF segment to routing segment mapping: for each routing segment in SPEF, corresponding geometries in drawn and litho-simulated layouts are found using SPEF node coordinates Shape rectilinearization: litho-simulated routing segments not rectilinear  perform rectilinearization similar to gate-poly SPEF database modification: parasitic change computed from lookup table for each slice (from rectilinearization)  parasitic network reduction  update SPEF database Device Analyses Motivation Overview Experiments & Results Interconnect Analyses Full-Chip Analyses Conclusions & Ongoing Work Drawn Layout (DEF) Drawn Layout (DEF) Objective-Specific Verilog Objective-Specific Verilog Lithosimulated Layout (GDS) Lithosimulated Layout (GDS) Device Analyses Device Analyses Interconnect Analysis Interconnect Analysis Parasitics (SPEF) Parasitics (SPEF) Library SPICE Netlists SPICE Netlists Objective Delay, Power, etc. Analyses Delay, Power, etc. Analyses Update Characterize For LVS Std. Cell GDS Std. Cell GDS Simulated Diffusion Contour Drawn Diffusion Boundary Drawn Poly a b Computed Diffusion Boundary Effective Diffusion Area Rectilinearize Midpoint-sum approximation Setup, Defocus = 0nmSetup, Defocus = 200nm Leakage, Defocus = 0nmLeakage, Defocus = 200nm < -8nm -7nm, -6nm -5nm, -4nm -3nm, -2nm +2nm, -3nm +4nm, +5nm +6nm, +7nm Cycle time 0.351ns Cycle time 0.363ns Leakage 1.488mW Leakage 2.789mW