1. Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State University CSE598A/EE597G Spring 2006

2. Mixed Signal Chip Design Lab ADC Glossary  DNL (differential nonlinearity) - measure of the maximum deviation from the ideal step size of 1 LSB

3. Mixed Signal Chip Design Lab ADC Glossary  INL (integral nonlinearity) - deviation of the entire transfer function from the ideal function

4. Mixed Signal Chip Design Lab ADC Glossary  Offset Error - difference between the ideal LSB transition to the actual transition point

5. Mixed Signal Chip Design Lab ADC Glossary  Gain Error - how well the slope of the actual transfer function matches the slope of the ideal transfer function

6. Mixed Signal Chip Design Lab ADC Glossary  Resolution - number of discrete values it can produce  Monotonic - digital output code always increases as the ADC analog input increases  Full scale - voltage range ADC can accept  Aliasing - due to unwanted signals beyond the Nyquist limit - to prevent, all undesired signals must be filtered

7. Mixed Signal Chip Design Lab ADC Glossary  SINAD (signal-to-noise and distortion) - RMS value of the output signal to the RMS value of all of the other spectral components below half the clock frequency  ENOB (effective number of bits) - dynamic performance of an ADC at a specific input frequency and sampling rate

8. Mixed Signal Chip Design Lab High Speed ADC Architecture  Flash ADC - highest speed - large # of comparators - large size - large power consumption - 8-bit maximum resolution

9. Mixed Signal Chip Design Lab High Speed ADC Architecture  Two-Step Flash ADC - SHA - D/A converter - subtractor - coarse flash ADC (MSB) - find flash ADC (LSB) - reduce # of comparators 2 N -1 2(2 N/2 -1)

10. Mixed Signal Chip Design Lab High Speed ADC Architecture  Pipelined ADC - multi-stage conversion - high speed - acceptable power - each stage has SHA, ADC, DAC, subtractor, Amp - different conversion step concurrently

11. Mixed Signal Chip Design Lab High Speed ADC Architecture  Folding ADC - no SHA (flash) - reduce # of comparators (two step flash) - small area, high speed - rounding problem

12. Mixed Signal Chip Design Lab  Time-Interleaved ADC - multiple ADCs in parallel high speed - offset/gain mismatch - phase skew High Speed ADC Architecture

13. Mixed Signal Chip Design Lab And More ADC Architectures  Algorithmic ADC - low power, small size, slow  Integrating-Type ADC - high accuracy, simple architecture, very slow  Successive Approximation ADC  R&C / C&R Type ADC  Interpolating ADC

14. Mixed Signal Chip Design Lab Design Consideration – Flash ADC  Large Input Capacitance parallel structure of 2 N -1 comparators limits speed performance large size buffer  Bubble / Sparkle no SHA, comparator mismatch… error in thermometer code solution : 3-input NAND

15. Mixed Signal Chip Design Lab Design Consideration – Flash ADC  Metastability input to ADC ≈comparator reference indeterminate output error solution : latch pipelining (extra gain) gray encoding (no signal split)

16. Mixed Signal Chip Design Lab  Clock Distribution and Timing clock travels long distance on a large ADC chip different delay, different loading  Kickback Noise disturbs reference Design Consideration – Flash ADC

17. Mixed Signal Chip Design Lab Design Consideration – Two-Step Flash ADC  Subtractor Gain without gain stage –output of subtractor = 1-LSB of coarse ADC –difficult comparator design (offset < 1-LSB of fine ADC) with gain stage –delay –mismatch between subtractor output and fine ADC input full scale missing code / nonmonotonicity

18. Mixed Signal Chip Design Lab Design Consideration – Two-Step Flash ADC  Nonlinearity  SHA V in residue V in residue including errors - gain mismatch - DNL, INL - offset -... analog input t level digitized by coarse ADC level sensed by subtractor t1t1 t2t2 ΔVΔV

19. Mixed Signal Chip Design Lab Design Consideration – Pipelined Flash ADC  MDAC (Multiplying D/A Converter) - performs subtractor, gain amplifier, S/H, and DAC

20. Mixed Signal Chip Design Lab Design Consideration – Pipelined Flash ADC  MDAC Operation removes offset (2 N -1)·C·V in +C·V in QiQi = =2 N ·C·V in VxVx

21. Mixed Signal Chip Design Lab Design Consideration – Pipelined Flash ADC  MDAC Operation Q f = 2 N ·C·DVref + C · V o from Q in =Q f, V o = 2N(V in -DV ref )

22. Mixed Signal Chip Design Lab Design Consideration – Folding ADC  Rounding Problem - only linear at zero-crossings limits resolution to ~10 bits

23. Mixed Signal Chip Design Lab Design Consideration – Folding ADC  Multiple Folds

24. Mixed Signal Chip Design Lab Two-Step Flash ADC Implementation  SHA  4-bit Coarse ADC  3-bit Fine ADC  Resistor-String DAC  Voltage Subtractor  Amplifier  Registers

25. Mixed Signal Chip Design Lab  Coarse ADC Two-Step Flash ADC Implementation Fat-Tree Encoder Bubble Correction

26. Mixed Signal Chip Design Lab  Coarse ADC Two-Step Flash ADC Implementation

27. Mixed Signal Chip Design Lab  Resistor-String DAC voltage scaling DAC simple fast small (under 8-bit) resistor mismatching Two-Step Flash ADC Implementation

28. Mixed Signal Chip Design Lab  Resistor-String DAC Two-Step Flash ADC Implementation 0001 1111

29. Mixed Signal Chip Design Lab  SHA Two-Step Flash ADC Implementation input output

30. Mixed Signal Chip Design Lab  Voltage Subtractor Two-Step Flash ADC Implementation V1 V2 8 x (V1-V2)

31. Mixed Signal Chip Design Lab  Things To Be Done voltage subtractor and gain amplifier - input voltage range for the subtractor - output offset - proper gain setting (input range of fine ADC) 3-bit fine ADC - identical to the 4-bit coarse ADC Two-Step Flash ADC Implementation