1. DSP Based Equalization for 40-Gbps Fiber Optic Communication Shahriar Shahramian

2. Problem & Motivation At high bit rates (> 10 Gbps) fiber optic channel’s impairments become prominent. Differential Mode Dispersion (in Multi Mode Fiber) & Polarization Mode Dispersion (in Single Mode Fiber) degrade signal quality over long haul fiber channels. Equalization techniques are required to achieve high bit rate over fiber optic channels.

3. Problem & Motivation II Some analog equalization techniques have been shown for 40-Gbps communication. Another possibility for equalization is digital equalization. The main challenge of high speed digital equalization is the design of the ADC at such high bit rates. Provided that high speed ADCs can be built, digital equalization is more accurate and offers more flexibility.

4. DSP Equalizer Block Diagram Detector & Pre-Amp Optical Fiber Ultra Fast ADC (40-GS/s) Adaptive Channel Equalizer Clock Recovery Equalized Data Adaptive Channel Equalizer Slicer + DFE FFE -

5. Flash ADC Block Diagram TIA INV TH DRV T/H Data Tree 1  16 Input StageTrack & Hold 16 GAIN Offset Amp. INV Comparators (16) Thermometer Code Output Clock Tree 1  16 16 S/H Clock External Clock Latch

6. THA Block Diagram TIA INV TH DRV Input StageTrack & Hold DRV Output Driver TIA Clock Distribution INV CLK DRV T/H

7. THA Die Photo Chip Area: –1.1mm 2 Technology: –0.18μm SiGe BiCMOS HBT –150/155 GHz f T /f max Foundry: –Jazz Semiconductor Clock Input (40 GHz) Data Input (DC – 20 GHz) Data Output DC & Biasing Input

8. THA Measurement Results OP ON Diff. Output OP Diff. Output Both data and clock input have been applied single ended. In Differential mode, the “in phase” clock feed- through signal is eliminated.

9. THA Measurements II Two tone signals at the input (separated by 100 MHz) have been used to measure the IM3 output power and the input compression point. An abstract has been submitted to CSICS 2005 based on this circuit as (to our best knowledge) the world’s fastest THA.