1. 0 - 1 © 2007 Texas Instruments Inc, Content developed in partnership with Tel-Aviv University From MATLAB ® and Simulink ® to Real Time with TI DSPs Class-D Audio Amplifier

2. Slide 2 © 2007 Texas Instruments Inc, System Description Input Stage Protection Circuit Buffer DC shift TMS 320F2808 Analog to PCM Conversion PCM to PWM Conversion Output Stage (Amplifier) Switching Amplifier H-Bridge LPF Audio Source

3. Slide 3 © 2007 Texas Instruments Inc, Audio Source The System 5V Power Supply 12V Power Supply

4. Slide 4 © 2007 Texas Instruments Inc, Analog to Digital (PCM) Conversion

5. Slide 5 © 2007 Texas Instruments Inc, PCM to Duty Cycle Conversion PCM Value Duty Cycle Shift Right 2 bits

6. Slide 6 © 2007 Texas Instruments Inc, PCM  PWM

7. Slide 7 © 2007 Texas Instruments Inc, PWM  Analog

8. Slide 8 © 2007 Texas Instruments Inc, H-Bridge Power Topology

9. Slide 9 © 2007 Texas Instruments Inc, TMS 320F2808 Input Circuit Functionality Input Stage Audio Source Analog Signal Amplitude Scaling DC removal Limits DSP Input Voltage 0 – 3.3 V Protection Circuit Buffer DC shift VRef for ADC ADC Analog to Digital (PCM) Conversion: 0-3.3 V  0-0xFFF

10. Slide 10 © 2007 Texas Instruments Inc, Input Circuit ReferenceVoltage 1.5 V Protection Circuit DC/DC Converter DC Removal +Volume Buffer+HPF To eZDSP-F2808 P8-1 GND

11. Slide 11 © 2007 Texas Instruments Inc, TMS 320F2808 Output Circuit Functionality Output Stage (Amplifier) Switching Amplifier H-Bridge LPF CPU EPWM PCM to PWM Conversion PWM Control

12. Slide 12 © 2007 Texas Instruments Inc, Output Circuit DriversProtection Full Bridge LPF EPWM1 - P8/9 EPWM2 - P8/11 PWM Inversion

13. Slide 13 © 2007 Texas Instruments Inc, Voltage Supply Input Stage eZDSP-F2808 Output Stage (Amplifier) 5 V 12 V DC/DC 3.3 V

14. Slide 14 © 2007 Texas Instruments Inc, Software Requirements TMS 320F2808 The input Signal in range 0~3V The Conversion Sequence starts on SOC signal Conversion Sequence capture 8 times the same channel with configuration: ADC Clock = 12.5 MHz S/H width = 320ns Generates Interrupt at the end of each Conversion Sequence At the Start: Initialize: CPU clock to 100MHz GPIO for PWM output Interrupt Vector (PIE) Set up ADC, PWM Enable HRPWM calibration Select Interrupt on ADC EOS Perform Endless Loop of HRPWM calibration PWM width is 1000 CPU clocks = 10us = 100KHz Timer in Up-count mode Values loaded at the end of PWM duty cycle When Timer is zero PWM is inactive When Timer = Value PWM is active Generate SOC signal at the start of each PWM duty cycle (Timer is zero) ADCCPUEPWM

15. Slide 15 © 2007 Texas Instruments Inc, Timer=CMP A Timer=zero CMPA Updated Timer=zero SOC is generated PWM Timer PWM1A Out SOC Impulse Interrupt Exit Interrupt Timing Diagram PWM2A Out PWM1A=Set PWM2A=Clea r ISR exit CMPA updated Analog to PCM Conversion ADC generates Interrupt End-of- Sequence PCM tp PWM Conversion CMPA Calculation PWM1A=Clea r PWM2A=Set

16. Slide 16 © 2007 Texas Instruments Inc, Simulink Model

17. Slide 17 © 2007 Texas Instruments Inc, Hardware Interrupt Module

18. Slide 18 © 2007 Texas Instruments Inc, ADC Configuration

19. Slide 19 © 2007 Texas Instruments Inc, ePWM1 Settings (1) Time-Base Settings: PWM Frequency 97.6 KHz (100 MHz/1024) with up-count mode timer

20. Slide 20 © 2007 Texas Instruments Inc, ePWM1 Settings (2) Counter-Compare: Load new Value at the start of PWM duty cycle Action-Qualifier: PWM= ‘1’ for TBCTR=0 PWM =‘0’ for TBCTR=CMPA

21. Slide 21 © 2007 Texas Instruments Inc, ePWM1 Settings (3) Event-Trigger: Generate SOC to module A at the start of PWM duty cycle

22. Slide 22 © 2007 Texas Instruments Inc, ePWM2 Settings (1) Time-Base Settings: PWM Frequency 97.6 KHz (100 MHz/1024) with up-count mode timer

23. Slide 23 © 2007 Texas Instruments Inc, ePWM2 Settings (2) Counter-Compare: Load new Value at the start of PWM duty cycle Action-Qualifier: PWM= ‘0’ for TBCTR=0 PWM =‘1’ for TBCTR=CMPA

24. Slide 24 © 2007 Texas Instruments Inc, ePWM2 Settings (3) Event-Trigger not activated