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Introduction of Holtek HT-46 series MCU
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Content Family of A/D Type MCU 1. Cost-Effective A/D type MCU
3. A/D with LCD type MCU 4. A/D with VFD type MCU 5. A/D with OPA type MCU Detail of HT46R24 1. Features of HT46R24 2. Block Diagram 3. Function Description(ROM, RAM, Interrupt, I/O, Timer, Buzzer, Oscillator, ADC, I2C, PWM, ….)
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Cost-Effective A/D Type MCU
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A/D Type MCU
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Features of HT46R24
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Block Diagram
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HT46X24 Pin Assignment
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Program ROM and Interrupt Vector
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RAM MAPPING
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63 Instructions Arithmetic Increment & Decrement Logic Operation
ADD, SUB… Increment & Decrement INC, INCA, DEC… Logic Operation AND, OR, XOR… Rotate RR, RRC, RL… Data Move MOV… Bit operation SET, CLR… Table Read TABRDC, TABRDL Branch JMP, SZ, RET, RETI… Miscellaneous NOP, SWAP, HALT…
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Arithmetic
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Logic, Increment, Decrement
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Rotate, Data Move, Bit Operation
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Branch
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Table Read ,Miscellaneous
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Indirect Addressing Indirect addressing Register: Memory Pointers:
IRA0,IRA1. Memory Pointers: MP0,MP1.
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Status Register
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I/O Structure
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Interrupt Interrupt has priority issue.
Once an interrupt subroutine is serviced, all the other interrupts will be block ( by cleaning the EMI flag). After the subroutine set the “RETI”, the EMI will be set again.
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Interrupt control register
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Interrupt Scheme
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Timer/Event Counter 0
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Timer/Event Counter 1
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Timer Control Register 0
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Timer Control Register 1
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3 modes available for the Timer/Counter
Timer Mode Event Counter Mode Pulse Width Mode
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4 steps to setup in the Timer Mode
Set to Timer Mode by writing 10 to TM1, TM0 Set the initial timer TMR value Enable the corresponding interrupt by setting the ETI and EMI bit Start the Timer by setting the TON bit of the TMRC
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5 steps to setup in the Even Counter Mode
Set to Event Counter Mode by writing 01 to TM1, TM0 Select TE=1 to count on the falling edge or TE=0 to count on the rising edge Set the Timer initial value into TMR Enable the corresponding interrupt by setting the ETI and EMI bits Start the Timer by setting the TON bit in the TMRC register
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5 steps to setup in the Pulse Width Measurement Mode
Set to Pulse Width Mode by writing 11 to TM1, TM0 Select TE=1 to measure a High Pulse Width and TE=0 to measure a Low Pulse Width Set the Timer initial value, TMR, usually set to 0H for Pulse Width Measurements Enable the corresponding interrupt by setting the ETI and EMI bits Start the Timer by setting the TON bit in the TMRC
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PFD and Buzzer PFD is programmable frequency divider.
PFD is pin shared with PA3(selected via configuration optional). Clock source of PFD is come from timer0 or timer1 overflow signal (selected via configuration optional). PFD output is controlled by switch on/off PA3.
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Watchdog Timer The watchdog timer is provided to prevent program uncontrollable . 3 clock sources can be selected as watchdog timing source: (by configuration) T1(fsys /4) , 32KHz RTC, WDT OSC output. At HALT, only WDT OSC or RTC oscillator is still running.
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Watchdog Register If watchdog timeout ,the system will be reset. The status bit “TO” will be set. There are two method of using software to clear watchdog timer (selected by configuration) : One instruction : CLR WDT Two instruction : CLR WDT1, CLR WDT2
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PWM PWM is Pulse Width Modulator.
There are two modes 6+2 or 7+1 selected by configuration. User can change the duty cycle by software by writing data to PWM0~PWM3 special data register. PWM function can be controlled On/Off by software. Enable PWM output : SET PD0 Disable PWM output : CLR PD0
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PWM 6+2 Mode
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PWM 7+1 Mode
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Analog to Digital Converter
The HT46R24 has a 10-bit ADC. ADC can be disabled by software. Max. 4 or 8 channels can input to the ADC. Channels set in ADCR by software ADC channels are pin-shared with Port B. As ADC input or Port B set in ADCR by software Input range is from 0 to VDD. Min. ADC clock period is 1 us. ADC sampling time is 32 ADC clocks. ADC convert time is 76 ADC clocks. Max. INL ± 1 LSB.
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ADC Convert Data Register
ADRL/ADRH are two registers to store the ADC convert data.
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A/D Convert Control Register
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A/D Convert Clock Source Register
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A/D Convert Timing Diagram
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I2C Bus Interface I2C bus is a bidirectional 2-wire serial interface.
SCL : serial clock pin. SDA : serial data pin. I2C output is of open drain . An external pull high resistor is needed. HT46 series I2C bus is only operates in Slave mode. For Master mode , user can implement by software.
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Data transfer on the I2C-bus
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I2C relative Registers I2C Slave Address Register - HADR
I2C Input/Output Data Register – HDR I2C Control Register –HCR. I2C Status Register – HSR.
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HADR Register
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HDR Register
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HCR Register
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HSR Register
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I2C Bus Communication STEP1 STEP2 STEP3
Write the slave address of the microcontroller to the HADR. STEP2 Set the HEN(bit7 of HCR) to 1 to enable the I2C bus. STEP3 Set the EHI(bit2 of INTC1) to 1 to enable I2C interrupt
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I2C Bus ISR Flow Chart
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HALT The system oscillator will be turned off.
All of the I/O ports and RAM remain unchanged. The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT oscillator. The PDF is set and the TO is cleared.
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How to wake up from HALT mode
External Reset External Interrupt Falling edge signal on port A WDT overflow
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RESET Power on reset Reset pin reset Low Voltage Reset WDT reset
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Power on Reset Power on reset 時間的定義是RESET 上升到VIH後到 MCU 開始執行程式這段時間
這段時間包含三大部分: 第一部分是RESET PIN 上升與 Oscillator 的啟動時間 第二部分是 Oscillator 的穩定時間 第三部分是MCU為了確保 clock 的正確性,再經過1024 個 clock 之後才將 clock 輸入系統 上述三段時間構成了 Power On Reset Time
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Low Voltage Reset SRC MCU 所搭載的 LVR 規格是 1.8V ~ 2.0V, typical 是 1.9V
如果 VDD 低於 LVR 的電壓範圍,且時間大於 1ms ,則會使 MCU 進入 reset 狀態,直到 VDD 大於 LVR 的範圍,才會讓 MCU 重新工作 但請注意 Note 1 的說明,1024 個 clock 的 delay 時間必須列入計算
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Register Initial Status (1)
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Register Initial Status (2)
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Register Initial Status (3)
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Application Circuit 其中 Oscillator 所連接的兩個電容(C1,C2),是為了調整震盪頻率的補償作用,一般的應用皆可省略,除非採用 1MHz 以下的 resonator 或是 crystal,才會用到這兩個電容 至於電容C* 的適當值,可以參考data sheet 的建議值。 VFD MCU 系統頻率的選擇透過 configure option共用三種方式: 是 RC Osc. 外掛電阻如圖右的第一格 是 Crystal Osc. 外掛 resonator 或是 crystal,如圖右的第二格
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Configuration Options
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Q & A
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