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SDSS7 - DSP and Backends Intro, 12 Jul 2013 Digital Signal Processing Basics and AO Back-Ends Luis A. Quintero Digital Section Head Electronics Department.

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Presentation on theme: "SDSS7 - DSP and Backends Intro, 12 Jul 2013 Digital Signal Processing Basics and AO Back-Ends Luis A. Quintero Digital Section Head Electronics Department."— Presentation transcript:

1 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Digital Signal Processing Basics and AO Back-Ends Luis A. Quintero Digital Section Head Electronics Department Arecibo Observatory

2 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Introduction to Digital Signal Processing

3 SDSS7 - DSP and Backends Intro, 12 Jul 2013 System - World time Quantity Transducer ELECTRICAL VARIABLE Resistance, Capacitance, Voltage, etc time Voltage Signal Conditioning Continuous Signal Acquisition - Transducers

4 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Continuous-time Signal (real signal) time Amplitude time Discrete-time Signal Amplitude Sampling

5 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Storage in Computers time 1V -1V + 0.40 - 0.90 … - 0.45 + 0.70 - 0.47 - 0.82 + 0.30 http://www.iusb.edu/

6 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Analog to Digital Converter – Quantization time + 0.40 - 0.90 … - 0.45 + 0.70 - 0.47 - 0.82 + 0.30 4 6 … 1 4 0 1 2 3 4 5 6 7 252 A/D …

7 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Analog to Digital Converter – Quantization time 4 6 … 1 4 2 5 2 Digital-to-Analog Converter D/A … http://www.iusb.edu/

8 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Digital Signal Processing System Digital-to-Analog Converter D/A … A/D Analog-to-Digital Converter … Computer Data Storage Data Processing - Math Operations - Filters - Fourier Transform - Data Format Computer (Digital System) - Micro Processor - DSP (MAC) - Logic Circuit - ASIC - PAL/CPLD - FPGA

9 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Sampling Rate – Analog to Digital time 1 Second Fs = 9 samples/second = 9Hz Fs = 19 samples/second = 19Hz Better signal reconstruction More computer memory / BW and $$

10 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Analog to Digital Converter - Clock Input A/D … clk ANALOG DIGITAL Clock for digital circuit Stable – jitter

11 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Resolution time Resolution: 3bits, 2 3 = 8 combinations Resolution: 4bits, 2 4 = 16 combinations Values from 0 to 7 Values from 0 to 15 Better signal quantization More computer memory and $$ 0 7 0 15

12 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Saturation Resolution: 3bits, 2 3 = 8 combinations Too much power to the ADC Saturation caused by interference (RFI) time 0 7

13 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Sampling – FT, Nyquist and Aliasing

14 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Sampling – FT, Nyquist and Aliasing Fs = 200Hz, Ts = 5ms, Fs/2 = 100Hz

15 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Processing – Adder = 1bit adder 4bit adder 4 4 5

16 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Processing – Multiplier 4 4 8 Multiplication by a Constant – Gain Multiplication by -1, Sign change Multiplication by a function – e.g. sin/cos - up/down conv. Things to consider Bit growing Precision – Approximation Errors

17 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Processing – Functions, e.g. sin/cos x[n] sin[n] x[n] * sin[n] n Phase Increment ADDR Mem - LUT DATA … DDS

18 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Processing – Synchronization clk latency

19 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Filtering – e.g. Finite Impulse Response (FIR)

20 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Auto Correlation

21 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Discrete Fourier Transform - DFT X[k] =F N x[n] FFT – Fast Fourier Transform, optimized DFT (butterflies)

22 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Examples with Signals Fourier Transform Saturation Averaging Clock Jitter

23 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, one tone

24 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, two tones

25 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, noise effect

26 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, averaging

27 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, longer transf.

28 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, Saturation

29 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Fourier Transform, Clock Jitter 0% Jitter 40% Jitter

30 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Applications in Radio Astronomy

31 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Gregorian Dome Receivers Ganesan, R. “Telescope Electronics”, May 2006

32 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Radio Frequency Signal Path

33 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Signal Transport – Intermediate Freq.

34 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Final Stage – Data Acquisition Data Sampling and Storage

35 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Bandpass Signals in IF

36 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Sampling - Nyquist Zones & Analog BW

37 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Wideband Arecibo Pulsar Processor (WAPP) 4 WAPPs 1 WAPP = 2 IF Channels 2 Correlators 1 Multiplexer 50/100 MHz BW auto / crosscorrelations Step attenuators Technical issues: Difficult to troubleshoot Obsolete parts

38 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Wideband Arecibo Pulsar Processor (WAPP)

39 SDSS7 - DSP and Backends Intro, 12 Jul 2013 WAPP Correlators (~1995) High Performance CMOS Correlator Chip (ASIC) 16 Chips per board Autocorrelation / Crosscorrelation 1024 Lags / chip 100MSPS each “Low Power” TTL compatible http://www.naic.edu/~astro/general_info/correlator/cmos.html

40 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Complex Sampling

41 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Arecibo L-band Feed Array 7 Receivers Dual Polarization 14 analog signals 1225 – 1525MHz 300MHz BW Designed by Germán Cortés Medellín (Cornell) Ganesan, R. “Telescope Electronics”, May 2006

42 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Complex Sampling Example: ALFA 12251525

43 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Mock Spectrometer / PDEV (~2007) Designed and developed by Jeff Mock 8 x AD9430, 12bits ADCs 2 x Xilinx Virtex II Pro FPGA 2 QDR Mem, 2M x 36 1x PowerPC Processor Flash & SRAM mems 2 x GbE, 2 x RS232 5 x SMA (clk, PPS, etc) LCD 128x64 pixels Digital Board Digitizers

44 SDSS7 - DSP and Backends Intro, 12 Jul 2013 PDEV – Architecture ADC GX 2VP70 PPC 440GX GX 2VP70 QDR 2Mx36 QDR 2Mx36 2 x GbE 2 x RS232 4 x SMA Flash / SRAM ADC PCIe x8 MGT PCIe x8 MGT

45 SDSS7 - DSP and Backends Intro, 12 Jul 2013 PDEV – Mock Spectrometer PFB/FFT 16-8k ADC0 GAIN/OFFSET SWITCH TEST SIGNAL 12 DDC (DDS, LPF) STOKESACCUMULATOR PACKETIZE CONFIGURATION REGISTERS PROC. INT. CW, Noise, CW + Noise

46 SDSS7 - DSP and Backends Intro, 12 Jul 2013 EALFA / PALFA Backend 14 PDEVs * 7 for 7 ALFA pixels (primary) 7 for 7 ALFA pixels (commensal) 14 File servers (4TB) We own in total 24 PDEVs DDC (DDS, Mixer, DLPF) PFB (up to 8192 channels) Stokes parameters Accumulation, Packing * http://www.naic.edu/~phil/talks/vc09/tel_Perf_datatking_09.ppt

47 SDSS7 - DSP and Backends Intro, 12 Jul 2013 GALFA Spectrometer / GALSPECT (~2004) Backend for the Arecibo L-band Feed Array (ALFA) multibeam receiver 7 beams, dual polarization Outputs * : Narrowband: 8192channels, 7MHz BW Wideband: 512 channels, 100MHz BW

48 SDSS7 - DSP and Backends Intro, 12 Jul 2013 PR Ultimate Pulsar Processing Instrument ( PUPPI) 100/200/400/800MHz BW Polyphase Filter Bank Dual Pol. 8 bit ADC Full Stokes 200MB per second recording (10GbE) 0-15.5dB Level Control PSRFITS data format 1xBee2 + 2xiBOB

49 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Recording Systems – Mark IV / 5A / 5C / RDBE Mark IV + Mark 5A: 1Gbps (125MB every second) RDBE + Mark5C: 4Gbps (500MB every second) eVLBI, AO-UPR- Centenial link: 155Mbps all time 512Mbps 24h-6h

50 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Roach Radar Backend – RRB Complex Baseband - Digital Down Converter (DDC) 50MHz bandwidth max. 2 x IF channels (polA/polB) Bit selection, 8/4bits 1.6Gbps max. data rate Doppler correction Programmable digital filter Hardware (three systems): ROACH – Signal Proc. katADC – 2x1.5Gsps@8bit RAID Server, dual 10GbE Fixed parameters: Summer 2012

51 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Analog v.s. Digital

52 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Down Conversion

53 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Digital Down Conversion

54 SDSS7 - DSP and Backends Intro, 12 Jul 2013 Questions?

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