1. Embedded Systems Development and Applications
Terrence Mak
The Chinese University of Hong Kong
CENG4480
Fall 2014/15

2. Analogue/digital conversions
Digital to analogue (DAC) conversion
Analogue to digital (ADC) conversion
Furthermore
Sampling-speed limitation
Frequency aliasing
Practical ADCs of different speed

3. Digital to Analogue (DAC) Conversion

4. Digital to analogue converter (DAC)
V+ref ( High Reference Voltage)
Output voltage = Vout(n)
Input code n
(NMAX bit Binary code) :
NMAX
(bit length)
DAC
V-ref (Low Reference Voltage)

5. DAC: basic equation At n=0, Vout(0) = V-ref At max. n_max= 2NMAX -1,
DAC output
V+ref
At n=0, Vout(0) = V-ref
At max. n_max= 2NMAX -1,
(E.g. NMAX=8, n_max=2^8-1=255)
Vout cannot reach V+ref ,
E.g. NMAX=8, n=0, 1, 2, … 255.
Some DACs have internal reference voltage settings, some can be set externally.
Code (n)

6. DAC: characteristics
Glitch: A transient spike in the output of a DAC that occurs when more than one bit changes in the input code.
Use a low pass filter to reduce the glitch
Use sample and hold circuit to reduce the glitch
Settling time: Time for the output to settle to typically 1/4 LSB after a change in DA output
???

7. Two DAC implementations
Type 1: Weighted Adder DAC
Easy to design, use many different Resistor values so it is difficult to manufacture.
Type 2: R-2R Resistive-Ladder DAC
Use only two R and 2R resistor values, easy to manufacture.

8. Type 1: Weighted Adder DAC (eg. N=8)
Resistor=2(N-i)*R
Resistor
R=2K
2R=4K 8K
16K
32K
64K
128K
128R=
256K
Ii=8 =28-1 *I1=27 * I1
i=8, 28-8 R = R
i=7, 28-7 R = 2R :
i=3, 28-3 R = 25R
i=2, 28-2 R = 26R
i=1, 28-1 R = 27R
Ii=8
Virtual earth
V-ref
Ii=1
I=Ii=1=Current=
(Vref -V-ref)/(28-1R)=(1/28-1)[(Vref -V-ref)/R]

9. Weighted Adder DAC (Cont’d)
When ith bit (e.g. N=8, i=7 , N-i=1) = 1
ith analogue switch (FET transistor) is turned on
Ii then flows through, Resistor 2N-iR

10. When n has only one bit on
Weighted Adder DAC (Cont’d)
When n has only one bit on
input side
feedback side

11. ** difficult to make because it uses a wide range of different Rs
Weighted Adder DAC (Cont’d)
When n has multiple on-bits
E.g. a 4-bit DAC, N=4. Input code=0101=n=n3+n1 (two bits are on)=binary{0100}+binary{0001}
** difficult to make because it uses a wide range of different Rs

12. Practical resistor network DAC and audio amplifier (not perfect but ok) Set R=2K
Data
Bit i
Ideal R
=28-iR
Practical
0(lsb) 1
256K
270K 2
128K
130K 3
64K
62K 4
32K
33K 5
16K 6 8K
8.2K 7 4K
3.9K
7(msb) 8 2K

13. Type 2: R-2R Resistive-Ladder DAC
Vertical
current
AD/DA (v.1b)

14. DAC type 2: R-2-R resistor-ladder
Required only R & 2R, easy for IC fabrication process
The most popular DAC
At each node, current is split into 2 equal parts:
One goes to V-ref; the other goes to the op-amp negative-feedback point
where
Since inputs V+ ~ V- of the opamp inputs are the same , the vertical current will not be changed by input code n

15. Exercise 1

16. Analogue to Digital (ADC) Conversion

17. Analogue to Digital Conversion (ADC)
V+ref
Input voltage = V)
N (MAX) bit
ADC
output code = n :
V-ref

18. ADC Major characteristics
n=converted code, V=input voltage,
The linearity measures how well the transition voltages lie on a straight line.
The differential linearity measures the equality of the step size.
Conversion time: between start convert and result generated
Conversion rate = inverse of conversion time

19. Analogue to digital converter example
Convert an analogue level to digital output
V-ref=0V, V=10mV.

20. ADC Type 1: Integrating or dual slope
Accumulate the input current on a capacitor for a fixed time and then measure the time (T) to discharge the capacitor at a fixed discharge rate.
1) S1->V1:Integrate the input on the cap. For N clock ticks
2) S1-> -Vref: restart clock (S2->counter) discharge C at know rate(governed by -Vref and R)
3) When the cap. is discharged to 0 voltage, the comparator will stop the counter.
problem – (very slow)??
AD/DA (v.1b)

21. Integrating dual slope ADC: Simplified Diagram
Discharge time for stopping counter by S2 depends on RC and Q

22. Type 2: Tracking ADC problem – also slow
The ADC repeatedly compares its input with DAC outputs.
Up/down count depends on input/DAC output comparison.
problem – also slow
AD/DA (v.1b)

23. Counter-Ramp ADC Use a counter to count from 0 to 2N-1
Use DAC to convert it into an analogue signal which is compared with the input analogue signal
Stop the counter when the input > the analogue signal generated by the counter.
Use a register to remember the count which is the required output.
Disadvantage: slow conversion speed (the worst case is count all steps before the DAC output voltage matches the analogue input voltage)

24. Counter-Ramp ADC (II)

25. Type 3 ADC : successive approximation
Faster, use binary search to determine the output bits.
problem – still slow although faster than types 1 & 2

26. Successive-Approximation ADC
Use successive-approximation register to replace the counter in counter-ramp ADC
Set D7 = 1; compare the output of DAC with input;
if Vin> Vout, Set D7 = 1; else set D7 = 0
Set D6 = 1; compare the output of DAC with input;
if Vin> Vout, Set D6 = 1; else set D6 = 0
Repeat until D0 is set
Take only eight clock periods to complete a conversion

27. Successive-Approximation ADC (II)

28. Successive-Approximation ADC (III)

29. Flow chart of Successive-approximation ADC
Yes, done

30. Type 4 ADC : Flash ADC (very fast)
Divide the voltage range into 2N-1 levels; use 2N-1 comparators to determine what the voltage level is
Use a 2N-1 input to N bit priority decoder to work out the binary number

31. Diagram of a flash ADC [1]

32. Type 4 ADC : Flash ADC (cont’d)
Very fast for high quality audio and video.
Very expensive for wide bits conversion.
Sample and hold circuit usually NOT required.
The number of comparators needed is 2N-1 which grows rapidly with the number of bits
E.g. for 4-bit, 15 comparators;
for 6-bit, 63 comparators.

33. Sampling and hold?
Why? It is because when a slow ADC is used to sample a fast changing signal only a short sampling point can be analyzed
Signal
Voltage
Vin
Vin(t1)
sampling
A fast changing signal
Vin(t1) held
and being converted
time
Data n
generated
Sample and
Hold and convert signal into data n t1

34. Sampling-speed limitation
Given the conversion time of an ADC is Tconv seconds, the maximum sampling rate is Fmax=1/T (Hz) .
E.g: ADC0801,
Tconv =114ns+P to ADC delay,
Fmax < 8.77KHz
For this sample rate the maximum frequency for the input is (Fmax/2) < 4.39KHz by Nyquist sampling theory.
Need to use a sample-and-hold circuit to freeze a fast changing input when using a low speed ADC to convert the signal.
For high speed conversion, use Direct-Memory-Access (DMA) to copy the data directly to P memory to reduce P to ADC delay.

35. Frequency aliasing
When the highest frequency of the signal Finput is greater than half the sampling ( Fsampling/2).
E.g. Finput =20KHz,
Fsampling must be over 40KHz.
Remedy: Use a low pass filter to cut off the input high frequency content before ADC sampling.

36. upper => sampling 6 times per cycle(fs=6f);
upper => sampling 6 times per cycle(fs=6f); middle => sampling 3 times per cycle(fs=3f); lower=> sampling 6 times in 5 cycles

37. Method to reduce aliasing noise
Use low pass filter to remove high frequency before sampling
Input voltage = V
Low
Pass
Filter:
fcorner=20KHz
ADC
Sampling
at 40KHz
output code = n :
e.g.
Max freq
=20KHz
Gain(dB)
-3dB cut off
Freq.

38. Summary Studied the operations of Digital/analogue conversions.
Studied the application of Digital/analogue converters.