1. OpenPET User Meeting: Status and Update Woon-Seng Choong, Jennifer Huber, William Moses, Qiyu Peng October 31, 2013 This work is supported in part by the Director, Office of Science, Office of Biological and Environmental Research, Biological Systems Science Division of the U.S. Department of Energy under Contract No. DE-AC02-05CH1231 and in part by the National Institutes of Health under grant R01 EB016104.

2. Outline Choong, IEEE NSS-MIC, October 31, 20132 Introduction Detector Boards Status Firmware and Software Status Website

3. OpenPET Vision Choong, IEEE NSS-MIC, October 31, 20133 Open Source Hardware, Firmware, and Software Schematics, Gerbers, BOM,… Standardized Architecture Compatible Alternate Hardware Software Readily Transportable Active User Community Share Software and Expertise Module, Calibration, DAQ, Display… OpenPET is the GATE of Nuclear Medical Imaging Electronics

4. OpenPET Hardware Architecture Choong, IEEE NSS-MIC, October 31, 20134 Support Board Detector Board Multiplexer Coincidence Host PC Data Control Detectors PP PP

5. Small System Choong, IEEE NSS-MIC, October 31, 20135 Detector Unit Host P C 1 Support Crate, Up To 8 Detector Boards Up to 256 Analog Inputs (64 Block Detectors) PC Interface Board Connects to PC 1 Support Crate, Up To 8 Detector Boards Up to 256 Analog Inputs (64 Block Detectors) PC Interface Board Connects to PC

6. Standard System Choong, IEEE NSS-MIC, October 31, 20136 Up To 8 Detector Units, 1 Coincidence Units Up to 2048 Analog Inputs (512 Block Detectors) Coincidence Interface Board Connects to CU Up To 8 Detector Units, 1 Coincidence Units Up to 2048 Analog Inputs (512 Block Detectors) Coincidence Interface Board Connects to CU CI-1 MB-1 CI-1 … (up to eight) CU DU0 DU1DU7 Host PC

7. OpenPET Hardware Choong, IEEE NSS-MIC, October 31, 20137 Power and Fans Detector Board Coincidence Interface Host PC Interface User IO Debugging Detector Unit 123456789101112 Support Board Complete and available Minor revision in progress Complete and available Under development First version of 16-ch Detector Board has been fabricated and tested. Minor revision in progress.

8. Support Crate Choong, IEEE NSS-MIC, October 31, 20138 FPGAs Power Fan 96-pin VME Connectors Host PC Interface Board User IO BoardDebugging BoardSupport Board 8 slots for Detector Boards 12-slot 6U VME 19” Rack Mountable Crate VME crate is available from Elma Electronics Inc. Electronics boards are available from Terasic Technologies VME crate is available from Elma Electronics Inc. Electronics boards are available from Terasic Technologies

9. Detector Boards Choong, IEEE NSS-MIC, October 31, 20139 16-Channel Detector Board - A scaled-down version to provide working DB to the users. - First version has been fabricated and tested. - Minor design improvements and fixes are in progress. - Final version to be available to users in a few months (early 2014). 32-Channel Detector Board (based on conventional design) - Design is almost complete. - Layout and fabrication to start in a few months. 32-Channel Detector Board (based on DRS4) - Design to start next year. - Expect to be available in 1-2 years.

10. 16-Channel Detector Board Choong, IEEE NSS-MIC, October 31, 201310 16-channel front-end circuitries IN0 IN1...... IN14 IN15 Only negative polarity inputs FPGA Altera Cyclone III 2 MB Memory 96-pin VME Backplane Connector Clock /Slice Out Clock /Slice In Digital I/O Singles Events Communication Bus (JTAG, SPI) Power Clock and Slice Trigger Control Lines Data

11. 16-Channel Detector Board Choong, IEEE NSS-MIC, October 31, 201311 Filter 7MHz FPGA Fast Comparator Threshold Adjust (1-2500 mV) x16 for each 16-ch Detector Board Slow Comparator Threshold Adjust (1 - 4000 mV) Fast Amp x10 OPA2694 (+/-5V) x-2 THS4303 (+/-2.5V) LTC6605-7 (+5V) MAX9602 MAX964 PECL to LVDS SY55855VKG SE to LVDS + - + - OPA4227 12-bit ADC ADS5282 IN

12. 16-Channel Detector Board Choong, IEEE NSS-MIC, October 31, 201312 Input Termination 16-channel Timing Chain 16-channel Energy Chain Digital I/O FPGA (Cyclone III) Logic Analyzer Connector 2 MB SRAM QUSB Connector Power Regulator External Clock Input JTAG Connector DIP Switch ADC AS Mode Connector

13. 16-Ch DB Evaluation Choong, IEEE NSS-MIC, October 31, 201313 17.0% fwhm15.5% fwhm With high-performance electronics, energy resolution was 15.8% and 14.4%. R-9800 6.15 x 6.15 x 25 mm 3 LSO crystals Ge-68

14. 16-Ch DB Evaluation Choong, IEEE NSS-MIC, October 31, 201314 7.8% fwhm6.1% fwhm R-9800 6.15 x 6.15 x 25 mm 3 LaBr 3 crystals Ge-68 With high-performance electronics, energy resolution was 5.6% and 4.7%. => 16-Ch DB has good spectroscopic performance.

15. 16-Ch DB Evaluation Choong, IEEE NSS-MIC, October 31, 201315 PET block detector: 12x12 array of 4x4x22 mm 3 LSO crystals, 4 Hamamatsu R-9800 PMTs

16. FPGA TDC Choong, IEEE NSS-MIC, October 31, 201316 1) Low resolution (500 – 1000 ps LSB) - Based on multi-sampling. -Inputs are sent to four registers connected to four internal clocks (400 – 500 MHz) with 90° phase difference. -Easy to implement and takes less resources. 2) High resolution (25 – 50 ps LSB) - Based on delay chain and wave union. -Include auto calibration to compensate for temperature and power supply variation. -More complex to implement and takes more resources. References: 1)J. Wu, S. Hansen, and Z. Shi, “ADC and TDC implemented in using FPGA,” Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Honolulu, HI, 2007, pp. 281–286. 2)J. Wu and Z. Shi, “The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay,” Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Dresden, Germany, 2008, pp. 3440–3446.

17. Firmware/Software Choong, IEEE NSS-MIC, October 31, 201317 System configuration and test (scripts) System configuration files System HW/FW DAQ configuration and DAQ (scripts) System HW/FW List mode data (with a head file) Data analysis and visualization (GUI and scripts) List mode data (with a header file) Data analysis reports System calibration and characterization (control console and scripts) Acceptable range definition ? First Release

18. Firmware/Software (“Oscilloscope” Mode) Choong, IEEE NSS-MIC, October 31, 201318 First Release: “Oscilloscope Mode” for Small System Two Command Line Executables to Configure System and Acquire Data First Release: “Oscilloscope Mode” for Small System Two Command Line Executables to Configure System and Acquire Data Detector BoardSupport Board Host PC ADC Readout Time Stamp Event Transfer InEvent Transfer Out Setup & Control Event Multiplexing Coincidence Processing Event Transfer Out Setup & Control Event Processing Event Transfer In Setup & Control Event Transfer InEvent Transfer Out Event Transfer In Completed ADC Readout Setup & Control Event Multiplexing Setup & Control In Development TDC Coincidence Processing Event Processing Not Needed for Oscilloscope Mode

19. Data Transfer Rate Via USB 2.0 Choong, IEEE NSS-MIC, October 31, 201319 A maximum sustained data transfer rate of ~ 43 MB/s is achieved (theoretical maximum is 60 MB/s for USB 2.0) Data rate (Million Bytes Per Second)

20. Firmware / Software First Release Choong, IEEE NSS-MIC, October 31, 201320 Necessary firmware on 16-Channel DB and SB to control the hardware and acquire list mode data via USB. - System configuration files to configure system. - List mode data is “Oscilloscope” mode. Command line executable with arguments to control/configure the system. Ex., opet_cmd … Command line executable to acquire data in list mode. Ex., opet_acq … Currently under development and testing. A major effort will go into documenting a User’s Guide before the first release. Will be released when the 16-channel Detector Board is made available.

21. Website (openpet.lbl.gov) Choong, IEEE NSS-MIC, October 31, 201321

22. Thank you for your attention