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Www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology.

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Presentation on theme: "Www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology."— Presentation transcript:

1 www.kit.edu Directors Prof. Dr.-Ing. K.D. Müller-Glaser Prof. Dr.-Ing. J. Becker Prof. Dr. rer. nat. W. Stork Institute for Information Processing Technology Karlsruhe Institute of Technology (KIT) CONDOR Plenary Berlin 02-03.05.2012

2 Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 2 | © Institute for Information Processing Technology

3 Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 3 | © Institute for Information Processing Technology

4 Milestones KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 4 | © Institute for Information Processing Technology

5 Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 5 | © Institute for Information Processing Technology

6 Status Hard and Software Library KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 6 | © Institute for Information Processing Technology ComponentStatus Leon3 – Control SystemImplemented AHB Multilayer MatrixImplemented Modulation ASIPImplemented FFT ASIPImplemented iFFT ASIPImplemented Internal DAC interfaceImplemented External DAC interfaceImplemented Internal ADC interfaceImplemented External ADC interfaceImplemented Demodulation ASIPNot Implemented Yet Synchronisation ASIPNot Implemented Yet Frequency Offset CorrectionNot Implemented Yet Channel Correction ASIPNot Implemented Yet PRBS ModulesNot Implemented Yet 25GS/s Polyphase Halfband DecimatorImplemented

7 Modulation ASIP 2 Samples per clock Software configurable configuration Unmodulated Pilot tone BPSK QPSK QAM 16 QAM 64 Software configurable pilot tones *depends on max. Configuration table and pilot table size KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 7 | © Institute for Information Processing Technology FPGA TypeLUTRegistersBRAMMax. Frequency Virtex-61986 962 2*212 MHz

8 (i)FFT ASIP Radix 2 (i)FFT ASIP 2 Samples per clock Max. 4 pipelined Radix 2 operations in a row Address calculation and Twiddle Factor calculation supports any FFT size KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 8 | © Institute for Information Processing Technology Max. FFT sizeLUTRegistersBRAMDSPMax. Freq. 256574444841520210 MHz 4096644346781620210 MHz 8192645547343220210 MHz

9 DAC/ADC Module Prepares data to analogue interfaces Serialization/Deserialization Preamble Storage 2ers complement or binary Clipping/rounding Cyclic Prefix Parallelism configurable by generics KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 9 | © Institute for Information Processing Technology

10 Transmitter design for Demonstrator Ca. 2 Samples per clock per stream PRBS Generator Generates data to be send (8 Samples per clock) 4 parallel data streams 1 Modulation ASIP (QAM 16) 2 (i) FFT ASIPs DAC Module Configured for 4 data streams (8 samples per clock cycle) Cyclic Prefix about 8 samples (16 samples worst case) 4Gb/s @125MHz FPGA clock FPGA TypeLUTRegistersBRAMDSP XC6VHX380T 44 2819%59 12024%14619%16418%

11 Receiver Special Components Digital Down Converter low pass filter to separate signal of interest decimation Synchronization time synchronization (results in wrong sample to start FFT with) frequency synchronization (results in orthogonal frequency problems) Correction local oscillator frequency offset (LOF offset) sampling oscillator frequency offset (SOF offset) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 11 | © Institute for Information Processing Technology

12 Digital Down Converter 4 halfband filter stages passband: 781,25 MHz decimation factor: 16 KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 12 | © Institute for Information Processing Technology FPGA TypeLUTRegistersBRAMDSPFrequency Virtex-629424406540192200MHz

13 Synchronisation Comparing autocorrelation and energy of received signal is used to determine the preamble. Phase difference of two consecutive, known symbols is used to compensate local frequency offset. KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 13 | © Institute for Information Processing Technology

14 Channel Correction Static version already implemented Correcting symbols with correction factor calculated by special symbol after preamble Planned Pilot symbol tracking Continuous feedback for correction factor KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 14 | © Institute for Information Processing Technology

15 Fault Tolerance Redundancy enabled by Modular design Multilayer metrix Spare ASIP instance ASIPs can be tested for functionality by software When disfunction is detected, ASIP will be replaced by spare ASIP of that type Broken ASIP might be repaired by reconfiguration (Single Event Upsets) Partial Reconfiguration Number of spare ASIPs can be broken down to one by using partial reconfiguration KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 15 | © Institute for Information Processing Technology

16 Fault Tolerance Redundancy using Partial Rekonfiguration KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 16 | © Institute for Information Processing Technology

17 Content Overview Project Status Milestones Status Hard-/Software Library Fault Tolerance of FPGA Hardware Demonstrator plans Prototyping Board and ADCs, DACs Demonstration Scenario KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 17 | © Institute for Information Processing Technology

18 Prototyping Boards Protyping Boards Estimated availability (October‘12) 2x XC6VHX380T 2x XC6VHX565T Sockets for Micram Ultra High Speed analogue converters DAC 25GS/s DAC 30GS/s Extension Boards with High Speed analogue converters DAC (MAX5881, 12-Bit, 4.3Gsps) ADC (ADC12D1800, 12-Bit, 3.6 GSPS) KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 18 | © Institute for Information Processing Technology

19 Demonstrator KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 19 | © Institute for Information Processing Technology

20 Vielen Dank für ihre Aufmerksamkeit Fragen? KIT – The cooperation of Forschungszentrum Karlsruhe GmbH and Universität Karlsruhe (TH) 20 | © Institute for Information Processing Technology - 11 Mai, 2011

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