1. A 107 dB DR, 106dB SNDR Sigma-Delta ADC Using a
Charge-Pump Integrator for Audio Application
The final year project presentation
The graduation thesis plea of XXX University
Student No.：
Sam, (DB028791); Hubert, (DB029125)
Supervisor：Prof. Sin-Weng Sai
Co-Supervisor：Prof. U Seng Pan

2. CON TENTS 1. Introduction 2. Basic theory of Sigma-Delta ADC
3. Target specification
4. Architecture Chosen
5. Charge Pump Integrator
6. Behavioral Model
7. Circuit Partial Design
8. Conclusion

3. 01
Introduction

4. Audio in life 1
A/D converter 2
Audio standard 3
Introduction

5. 1 2 3 ADC Introduction Audio in life A/D converter Audio standard
Analog
Digital
Signal:
Continuous signal which represents physical measurements.
Discrete time signals generated by digital modulation.
Example:
Human voice in air, analog electronic devices.
Computers, CDs, DVDs, and other digital electronic devices.

6. 1 2 3 ADC Introduction Audio in life A/D converter Audio standard
Increase the quality,
reduce the noise and Cumulative distortion.
Save energy,
use converter instead of the amplifier in transmission.
Information safety,
Given the timing information, the transmitted waveform can be reconstructed

7. 1 2 3 Introduction Audio in life A/D converter Audio standard
People’s hearing range
Frequency range: 20~20k Hz
Sound Pressure Level(SPL)
= 𝐿 𝑃 =20 log 𝑃 𝑟𝑚𝑠 𝑃 𝑟𝑒𝑓 𝑑𝐵 ; 𝑃 𝑟𝑒𝑓 =2𝑢𝑝𝑎 human ear's audible sounds is from 0 dB SPL (hearing threshold) to 140 dB SPL (pain threshold) 

8. 1 2 3 Introduction 44.1 KHz 16bit about 96dB dynamic range
Audio in life 1
A/D converter 2
Audio standard 3
Introduction
Compact Disc Digital Audio (CDDA or CD-DA) is the standard format for audio Compact Discs. The standard is defined in the Red Book
44.1 KHz 16bit about 96dB dynamic range
symphony orchestra 110dB SPL
Library 30 dB SPL
110 dB - 30 dB = only 80 dB real dynamic range if you brought the orchestra into your home
Good enough for listeners !

9. ？ 1 2 3 Introduction Audio in life A/D converter Audio standard
An professional requires more during mixing and mastering. Multiplying that noise by a few thousand times eventually becomes noticeable.
Keep the accumulated noise at a very low level ! ？
16 bit enough?
Going from a whisper to a scream requires a large dynamic range. When we create and produce music we can use the dynamic range to aid musical expression. We can have gently plucked guitars and booming techno bass lines all in one song.
undetectable during playback
Modern work flows may involve literally thousands of effects and operations.
Once the music is ready to distribute, there's no reason to keep more than 16 bits.

10. Basic theory of Sigma-Delta ADC02
Basic theory of Sigma-Delta ADC

11. 1 2 Basic theory High resolution Low bandwidth Different ADC
Key features 2
Basic theory
High resolution
Low bandwidth

12. 1 2 Basic theory Different ADC Key features
Signal to noise ratio for Nyquist ADC
𝑆𝑁𝑅| 𝑑𝐵 =10𝑙𝑜𝑔 𝑃 𝑠𝑖𝑔𝑛 𝑃 𝑛𝑜𝑖𝑠𝑒
where Psign and Pnoise are the power of the signal and the power of the noise in the band of interest.
Sine wave as example:
𝑃 𝑠𝑖𝑛𝑒 = 1 𝑇 0 𝑇 𝑋 𝐹𝑆 𝑠𝑖𝑛 2 2𝜋𝑓𝑡 𝑑𝑡≈ 1 𝑇 0 𝑇 𝑋 𝐹𝑆 𝜋𝑓𝑡 2 𝑑𝑡 = (∆∙ 2 𝑛 ) 2 8
𝑃 𝑄 = ∆ 2 12
∴𝑆𝑁𝑅 𝑠𝑖𝑛𝑒 | 𝑑𝐵 = 6.02∙𝑛+1.78 𝑑𝐵
Every bit of quantizer improves the SNR by 6.02 dB!!!

13. 1 2 Basic theory Oversampling (OSR) Noise shaping (Order)
Different ADC 1
Key features 2
Basic theory
Oversampling
(OSR)
Noise shaping
(Order)

14. 03
Target specification

15. Products’ use 1
Our target 2
Target specification

16. 1 2 Target specification Products’ use Our target
Audio Sigma-Delta ADC From TI Company
NAME
SNR
Normal products
pcm1870
90dB
pcm1808
99dB
pcm1851a
101dB
pcm1803a
103dB
From the table, listing some the audio ADCs use in car audio system. The SNR performance is 99dB.
Thus We set our target as 105dB SNR, After setting the target, the structure of the ƩΔ ADC will be chosen to build the system.

17. 04
Architecture Chosen

18. 1 2 Architecture Chosen Architecture Quantizer and OSR
Single Loop Architecture
CIFB – Cascade Integrators with Distributed Feedback
CIFF – Cascade Integrators with Distributed Feed-forward
CRFB – Cascade Resonator with Distributed Feedback
CRFF – Cascade Resonator with Distributed Feed-forward

19. 1 2 Architecture Chosen CIFB CIFF Architecture Quantizer and OSR
-ai = bi for i ≤ 3
-b4 = 1
NTF
CIFF
- b1 = b4 = 1

20. 1 2 Architecture Chosen CRFB CRFF Architecture Quantizer and OSR
-ai = bi for i ≤ 3
-b4 = 1
NTF
CRFF
- b1 = b4 = 1
Further increase SNR by optimizing NTF zero

21. 1 2 Architecture Chosen Architecture Quantizer and OSR Feedforward
Feedback
Only one DAC required
Requires many feedback DACs
Needs an extra adder
No extra adder
First integrator is fastest
Last integrator is fastest
First opamp is power hungry
With Resonator
Without Resonator
Advantage
Higher SNDR
Simpler Structure
Disadvantage
More Complex Structure (Resonator)
Lower SNDR

22. Architecture Chosen
Architecture 1
Quantizer and OSR 2
1.5 Bit Quantizer 01
Higher SNR
Ensure linearity
OSR=256
Higher SNR
Decrease the Thermal Noise 02 05 03
3rd order architecture
Higher SNR
A single loop 3rd order CRFB Σ-Δ ADC with 1.5 bit quantizer and 256 OSR are designed.

23. Charge Pump Integrator05
Charge Pump Integrator

24. 1 2 Charge Pump Integrator Introduction Conclusion
CRFB architecture using conventional SC integrator
CRFB architecture using CP SC integrator

25. 1 2 Charge Pump Integrator Conventional Charge-pump Introduction
Conclusion 2
Conventional
𝐶𝑠/𝑘 Φ2
Charge-pump
As upper mention, in order to get high resolution system, large OSR and large sampling capacitor are require to reduce the thermal noise which constraints the power consumption of op-amp. Moreover, one of the main constraints of the chosen structure CRFB is the high requirement of first op-amp which requires high DC gain as well as high power consumption. In this project, a special integrator called charge-pump integrator shown in above figure is used to improve the power efficiency. Φ2

26. 1 2 Charge Pump Integrator Conventional Charge-pump Introduction
Conclusion 2
Conventional
Charge-pump
𝐶𝑠/𝑘
𝑃𝑂𝑊 𝑂𝑃 ∝ 𝑔 𝑚
𝐶 𝐿 = 𝐶 𝑠 𝑘+1 + 𝐶 𝑙
𝐶 𝐿 ′= 𝐶 𝑠 2 𝑘+2 + 𝐶 𝑙
𝑔 𝑚 = 𝜔 −3𝑑𝐵 𝐶 𝐿 𝛽
𝛽= 1 𝑘+1
𝛽′= 2 𝑘+2
As upper mention, in order to get high resolution system, large OSR and large sampling capacitor are require to reduce the thermal noise which constraints the power consumption of op-amp. Moreover, one of the main constraints of the chosen structure CRFB is the high requirement of first op-amp which requires high DC gain as well as high power consumption. In this project, a special integrator called charge-pump integrator shown in above figure is used to improve the power efficiency.
𝐶 𝐿 𝛽 ′ ≈ 𝐶 𝐿 4𝛽
𝐶 𝐿 𝛽 = 𝐶 𝑠 + 𝐶 𝑙 (𝑘+1)
( 𝐶 𝐿 𝛽 )′= 𝐶 𝑠 4 + 𝐶 𝑙 ( 𝑘 2 +1)
𝑔 𝑚 ′ = 𝑔 𝑚 4
𝑃𝑂𝑊 𝑜𝑝 ′ = 𝑃𝑂𝑊 𝑂𝑃 4

27. S W O T 1 2 Charge Pump Integrator STRENGTH WEAKNESS OPPORTUNITY
Introduction 1
Conclusion 2
STRENGTH
WEAKNESS
Reduce the power consumption of the amplifier
Need double supply voltage
(two 0.25um transistor) S W O T
OPPORTUNITY
THREATS
Easier to implement by adding capacitor
May cause unmatched problem and high requirements to other parts

28. 06
Behavioral Model

29. 1 2 Behavioral Model The 3rd order CRFB with noise block in Matlab
Ideal Model 1
Model with Non-idealities 2
Behavioral Model
The 3rd order CRFB with noise block in Matlab

30. 1 2 Behavioral Model The main non-idealities Ideal Model
Model with Non-idealities 2
Behavioral Model
The main non-idealities
Operational amplifier non-idealities:
Bandwidth of Op-amp;
Slew rate of Op-amp;
Operational amplifier saturation voltages.
Thermal noise of Switch Capacitor structure.
noise of op-amp.
clock jitter at the input sampler.

31. 1 2 Behavioral Model DC gain requirement of first op-amp
Ideal Model 1
Model with Non-idealities 2
Behavioral Model
DC gain requirement of first op-amp
Finite DC gain
SNR
80dB
134.8dB
60dB
58dB
132.3dB
54dB
128.1dB
50dB
120.4dB
Repeat the operation to obtain behavioral model of the system

32. 1 2 Behavioral Model Behavioral Model of The Project Ideal Model
Model with Non-idealities 2
Behavioral Model
Behavioral Model of The Project
Sigma-delta Parameter
SNR (dB)
Ideal modulation
134.8
Finite DC gain (A=58dB, 58dB, 50dB)
130.6
Finite bandwidth(GBW=100MHz)
Finite Slew-rate (SR=60V/us)
Saturation voltages (|Vmax|=1V)
Sampling Jitter (Δ𝜏=17𝑝𝑠)
130.7
Switch (kT/C) noise (Cs=10pF)
110.4
Input-referred operational amplifier noise (Vn=1.5uV)
108
Including all of the non-idealities

33. The gain of first Op-amp(dB) simulation result of Cadence(dB)
Ideal Model 1
Model with Non-idealities 2
Behavioral Model
In cadence simulation, the first Op-amp gain requirement is 58 dB for 133dB SNR, now change the architecture:
The gain of first Op-amp(dB)
simulation result of Cadence(dB) 54
133 50 48 46
132 42
130
It is clearly found that the requirement of first Op-amp is reduced

34. Circuit Partial Design07
Circuit Partial Design

35. 1 4 2 3 Circuit Partial Design 1st CMFB Op-amp Design Op-Amp:
Optimization 2
Quantizer 3
Switch 4
Circuit Partial Design
Op-amp Design
1st
Op-Amp:
Main structure
Bias Circuit
Switched-capacitor CMFB
CMFB

36. 1 4 2 3 Circuit Partial Design 2nd 3rd Op-amp Design Op-amp
Optimization 2
Quantizer 3
Switch 4
Op-amp Design
2nd
3rd

37. 1 2 3 4 Circuit Partial Design Zero Optimization Op-amp Optimization
Quantizer 3
Switch 4
Circuit Partial Design
Optimization 2
Zero Optimization
For the CRFB structure, it needs a local feedback from third integrator output to second integrator input to make up a resonator which effects the zero.
Q 2 = V 𝑜3 𝐶 1 ||( 𝐶 2 + 𝐶 ∙ 𝐶 2 𝐶 3 + 𝐶 2
Q=g∙ V 𝑜3

38. 1 4 2 3 Circuit Partial Design 1.5 Bit Quantizer Op-amp Optimization
Switch 4
Circuit Partial Design
1.5 Bit Quantizer

39. 1 4 2 3 Circuit Partial Design Op-amp Optimization Quantizer Switch
CMOS switch
It is often used very large or small voltage input, under such situation, the transmission resistor will change critically

40. 1 4 2 3 Circuit Partial Design Op-amp Optimization Quantizer Switch
Bootstrapped Switch
To obtain constant conductance, the bootstrap technique can be used to keep the gate-source voltage at a certain value.

41. 08
Conclusion

42. 1 2 3 Conclusion System Performance Comparison Summary
107dB Dynamic Range
Output PSD for the system
Measured SNDR versus input amplitude
Technology
Sampling Frequency
Bandwidth
Peak SNDR
Power Consumption
FOM
65nm CMOS
10.24MHz
20kHz
106dB
1.332mW
204f/conv.

43. 1 2 3 32.4% Conclusion System Performance Comparison Summary
Transistor level comparison of system using CP And Conventional CP
Conventional
Peak SNDR
106dB
102dB
Power consumption
1.332mW
1.972mW
FOM
204f/conv.
479f/conv.
32.4%
Power consumption
32.4% decrease because of first stage
It achieves a higher SNDR but cost less power by using CP integrator

44. Comparison with Other Σ-Δ ADC
System Performance 1
Comparison 2
Summary 3
Conclusion
Comparison with Other Σ-Δ ADC
This work
JSSC/06
CICC/11
TCAS-1/13
JSSC/09
JSSC/08
JSSC/03
[1]
[2]
[5]
[4]
[3]
[6]
Tech
[um]
0.065
0.13
0.18
0.35
Supply
[V]
1.0
1.2
0.7
0.9 2
Input Range
[Vpp-diff]
0.4
1.1 /
OSR
256
300 64
128
100
154 BW
[kHz] 20 24 10
SNDR
[dB]
106 95
87.8 81 89
105
Power
[uW]
1332
2200
371
148 36
1500
68000
FOM
[fJ/conv.]
204
11200
170
369 98
1360
11700

45. 1 2 3 Conclusion For audio application => high SNDR (target ≥105dB)
System Performance 1
Comparison 2
Summary 3
Conclusion
For audio application => high SNDR (target ≥105dB)
Suppress the in-band noise (oversampling and noise shaping)
3rd CRFB Sigma-Delta modulator architecture using CP integrator is selected
As a result, with a full-scale input of 900mVpp differential the CRFB ADC using charge-pump integrator achieves 106 dB SNDR and 107dB dynamic range in audio bandwidth (20kHz), while consuming 1.332mW power.

46. Reference
Dorrer, L., et al. "A 2.2 mW, continuous-time sigma-delta ADC for voice coding with 95dB dynamic range in a 65nm CMOS process." Solid-State Circuits Conference, ESSCIRC Proceedings of the 32nd European. IEEE, 2006.
Liu, L., et al. "A 95dB SNDR audio ΔΣ modulator in 65nm CMOS." Custom Integrated Circuits Conference (CICC), 2011 IEEE. IEEE, 2011.
M. G. Kim, G.-C. Ahn, P. Hanumolu, S.-H. Lee, S.-H. Kim, S.-B. You,J.-W. Kim, G. C. Temes, and U.-K. Moon, “A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1195–1206, May 2008.
Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 458–472, Feb
Nilchi, Alireza, and David A. Johns. "A low-power delta-sigma modulator using a charge-pump integrator." Circuits and Systems I: Regular Papers, IEEE Transactions on 60.5 (2013):
Yang, YuQing, et al. "A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm 2." Solid-State Circuits, IEEE Journal of 38.12 (2003):

47. THANK YOU !