1. Leakage Modeling and Reduction Amit Agarwal, Lei He et. al Presenters: Qun Gu Ho-Yan Wong Courtesy of Lei He

2. Outline Introduction Circuit level leakage reduction System level leakage reduction Coupled leakage and thermal simulation and management

3. Power Trends

4. Circuit Power Dynamic Power: determined by circuit performance requirement etc. The percentage is getting smaller. Short_Circuit Power: Both PU and PD circuit partially conduct. Small percentage. (<10%) Leakage Power: Increasingly important, and many issues dependent, such as device geometry, temperature, doping, processing and data pattern dependent, etc. It is very complicated and worthy to study more to improve it.

5. Leakage Power Sources Subthreshold leakage Reverse Biased Junction BTBT Leakage Gate Leakage

6. Leakage Dependences

7. Circuit Techniques to Reduce Leakage Design Time Techniques  Dual threshold CMOS Run Time Techniques  Standby Leakage Reduction Techniques Natural Transistor Stacks Sleep Transistor (MTCMOS) Forward/Reverse Body Biasing (VTCMOS)  Active Leakage Reduction Techniques Dynamic Vth Scaling (DVTS)

8. Dual Threshold CMOS Low Vth for critical path High Vth for non-critical path Concerns: It is not so straigtht forward to do this. Sometime tradeoff exist between high Vth and low Vth applications. Vth variation cannot be always success at low voltage supplies. Increasing the number of critical paths will sometimes hurt circuit performance. Adjust Vth approaches in fabrication: Adjustment of tox (the higher tox, the higher Vth) How?

9. Natural Transistor Stacks Reduce the leakage by stacking the devices. Trade off between speed and power Data pattern determined Trade off with other leakage power ( gate leakage) How ? Concerns:

10. Sleep Transistor (MTCMOS) How? Inserts an extra series connected transistor (sleep transistor with high Vth) in the PU/PD path of a gate and turns it ‘off’ in the standby mode of operation. Disadvantages: Increase area and delay Data retention problem Hard to turn on completely at very low supply voltages

11. Improvements for MTCMOS -- VRC Virtual power/ground Rails Clamp (VRC)  Solves data retention problem with diodes  Virtual level changes are clamped  Allow data to be retained in SRAM arrays Alternatives: Super cutoff CMOS (with low Vth) (SCCMOS) In standby mode, PMOS gate is Vcc+0.4v, NMOS is Vss-0.4v to fully cut off leakage.

12. Forward/Reverse Body Biasing (VTCMOS) RBB (Reverse Body Bias): zero body bias in active mode, a deep reverse bias in standby mode. FBB (Forward Body Bias): high Vth in standby mode, forward body biasing to achieve better current drive in active mode. Disadvantages: Increase PN junction reverse leakage Scaling down technology worsen short channel effects and weaken the Vth modulation capability Disadvantages: Larger junction capacitance High body effect for stack devices Technology improvement for high Vth: Different doping profile Higher work function materials

13. Dynamic Vth Scaling (DVTS) The lowest Vth is delivered (NBB-no body bias) if the highest performance is required. When the performance demand is low, clock frequency is lowered and Vth is raised via RBB to reduce the run time leakage power dissipation. How? When critical path replica frequency is less then reference CLK, adjust bias to decrease Vth. Otherwise adjust bias to increase Vth. Results:

14. Process Variation and Leakage I DSAT and I OFF variation measured (150nm process). Variation Sources: Channel length Transistor width Oxide thickness Flat-band voltage Random dopant effect The effects of larger spread of leakage: Robustness of logic circuits. Circuit design margin. Circuit Techniques for Compensation Process Variation: Adaptive body biasing for process compensation Process variation compensation in dynamic circuits

15. Adaptive Body Biasing for Process Compensation Due to the worsening parameter fluctuation: Some dies may not meet the target frequency. Others exceed the leakage power constraints. How? The slow dies which fail to meet the desired frequency can be forward body biased to improve performance which paying more leakage power. On the other hand, excess leakage dies can be reverse body biased to meet the leakage power specifications. Effects: So adaptive body bias reduces the spread of the die frequency distribution by 7X, compared to a conventional zero body bias.

16. Process Variation Compensation in Dynamic Circuits (I) Programmable keeper size scheme: A desired effective keeper width can be chosen among {0, W, 2W, …7W} according to the control bit. Dynamic Circuits need keepers to compensate leakage current to keep data. The consideration for keepers size: Unnecessary large keeper size will hurt circuit performance Excess leakage dies can not meet the robustness requirements without enough keeper size.

17. Process Variation Compensation in Dynamic Circuits (II) Simulation Results: 5X reduction in the number of robustness failing dies and 10% improvement in average performance. Variation spread of the robustness and delay distribution is reduced by 55% and 35%

18. System Level Leakage Reduction Motivation Leakage characteristics and reduction Coupled leakage and thermal simulation and management  Power and thermal simulation  Dynamic power and thermal management  Vdd scaling with cooling selection

19. Motivation Leakage current has increased due to scaling in V t, L, and t ox Leakage power becomes more important due to high leakage devices and low activity rates Leakage power depends greatly on temperature

20. Power States at System Level 3 Power states defined at system level: 1. Active Mode – circuit in operation; P= P d + P s 2. Standby Mode – circuit is idle but ready to execute; P= P s 3. Inactive Mode – circuit is deactivated by leakage reduction techniques; P < P s

21. System Level Leakage Power Modeling Early model: P s = V dd * N FET * k design * I leakage Later model, with application of 2 leakage power reduction techniques (later): P s = V dd * N gate * I avg

22. Leakage Power Characteristics Minimum Idle Time (M.I.T) M.I.T. = {E s-i + E i-s – P i * (t s-i + t i-s )} / (P s – P i ) Idle Period Leakage power reduction is useful only when Idle Period > M.I.T.

23. Runtime Leakage Reduction for Caches Caches dissipate large amount of leakage power due to large SRAM array structures Different techniques are developed to reduce L1 cache P s, e.g. DRI, SWAY Basic principle is to dynamically turn off partial cache array structure

24. P s Reduction for L2 Caches L2 cache has much larger miss penalty, so approach for L1 can not be directly applied Use VRC to reduce P s, and use time-out based control mechanisms to shutdown L2-cache data portion Time out threshold could be fixed (FTO), dynamic, or by feedback control (FCTO)

25. P s Reduction for L2 Caches cont’d FTO  Time out threshold is set as M.I.T. FCTO  Adjust the time-out threshold with the proportional- integral (PI) feedback controller  Update time-out threshold according to N: L2 cache miss rate in previous time window T old : Time-out threshold in previous time window  New timeout threshold T = T old + (N – Setpoint) * Gain

26. Circuits for FCTO Timeout controller Threshold controller TagIndexBlock offset Tag potion Check for tag match Data potion Mux hit/miss Timeout controller Request address: Hit? hit/miss Wakeup signal Yes Threshold controller = Shutdown signal Counter Threshold register -X+ N miss setpointgain Threshold output Data word Wakeup/ shutdown signals

27. Comparison of L2 Leakage Reduction Power reduction (%)Performance penalty (%) BenchmarkFTOFCTOSWAYDRIFTOFCTOSWAYDRI go52.2163.8057.5556.791.061.109.957.39 li12.9227.8726.6426.560.931.077.287.71 equake35.7548.6146.4045.710.841.019.7310.58 art0.072.202.172.180.370.923.183.14 Time-out (FTO and FCTO) achieve much smaller performance penalty Targeting at 1% performance loss, FCTO obtains more power reduction than FTO does.

28. System Level Leakage Reduction Motivation Leakage characteristics and reduction Coupled leakage and thermal simulation and management  Power and thermal simulation  Dynamic power and thermal management  Vdd scaling with cooling selection

29. Temperature Aware Computing Initial conditions (T, delay) uArch Floorplan packaging Workload (e.g. Spec 2k) Adjusted conditions (T, delay) Performance simulator (e.g. SimpleScalar, IMPACT) Dynamic power estimation (e.g. Wattch) Leakage estimation Coupled power and thermal simulator (e.g. PTscalar, PowerImpact) Temperature-aware architecture techniques (DVS, DTM, reconfigurability power model, GALS, etc)

30. Leakage Model with Temperature Scaling Exponential scaling based on BSIM3v3 Logic circuits in ITRS 100nm technology: Memory units in ITRS 100nm technology:

31. Based on SPICE level 1 model, transistor saturation current I sat is proportional to  We obtain  ITRS 100nm technology T=60 o C T=80 o C T=100 o C Delay with Vdd and Temperature Scaling

32. Thermal Modeling For the lumped RC thermal circuit  Thermal resistance R th : the ability to remove heat to the ambient in steady-state condition  Thermal capacitance C th : capture the delay between a change in power and the corresponding change in the temperature  Thermal time constant τ= R th * C th Distributed model is needed for accurate solution

33. Coupled Power and Thermal Simulation Simulate time step t s < 0.5% of time constant (~10 6 cycles) will give negligible temperature and power calculation errors Clock gating reduces dynamic power and also leakage energy Leakage energy changes with operation temperature

34. Leakage Power at Different Temperature uP similar to DEC Alpha 21264 and with clock gating Leakage differs by up to 2X between 80 o C and 110 o C  Differs for different applications too. Coupled thermal and power simulation is a must 0% 20% 40% 60% 80% 100% 3585110 Dep3585110 Dep Temperature ( o C) Normalized total power Dynamic powerLeakage power Benchmark artBenchmark gcc 100nm, 3.33GHz, 1.2V

35. Thermal Runaway Thermal runaway is caused by the positive feedback loop between on-resistor, temperature, and power Also a result of the interaction between leakage power and temperature  Component temperature ↑  leakage power ↑ exponentially  temperature ↑  If cooling not adequate, both keep increasing

36. Thermal Runaway cont’d Assume no throttling and constant power consumption, conditions for thermal runaway is equivalent to d 2 T/dt 2 > 0 Lowest temperature to meet TR criteria is runaway temperature

37. Dynamic Power and Thermal Management (DPTM) Goal: Maximize throughput subject to maximum on-chip temperature constraint For each time window = X cycles, stop or throttle instruction fetch in cycles  0<=δ <=1 Feedback controller (Proportional Integral) to adjust δ:  For each time window, updateδ according to Current maximum on-chip temperature δ in previous time window

38. Dynamic Power and Thermal Management (DPTM) Fetch toggling toggles I-cache, I-TLB, branch prediction and decode units Dynamic frequency scaling (DFS) and Dynamic Voltage Scaling (DVS) adjust the clock freq and V dd  stall Activity migration move activities to another component copy of lower temperature

39. Need for Temperature Dependent Leakage Model Dynamic thermal management using fetch toggling with PI feedback controller Implemented 2 models: simple (fixed P s ) and accurate (P s is temp. dependent)

40. Validation of PI-based DPTM Compared with two practices:  No dynamic management Lower Vdd to avoid thermal violations  Cooling down If reaching the thermal threshold, stop the whole processor until the maximum temperature is X o C lower than the threshold X = 5 in our experiments

41. System Performance DPTM by feedback control may improve throughput by up to 11% compared to no DPTM case DPTM allows designing for common workload but not the worst case => thermal speculation

42. Active Cooling Direct water-spray cooling  Thermal resistance 0.067 compare to 0.8 for conventional heatsink Microchannel with liquid coolant, …

43. Impacts of Water Cooling Increases the maximum throughput by 30% Improves power efficiency by 9% and slows down the decay of power efficiency

44. References Amit Agarwal et. al, “Leakage Mechanisms and Leakage Control for Nano-Scale CMOS Circuits”, Purdue University. Lei He et. al, “System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage”, UCLA.