1. 1 4-BIT ARITHMETIC LOGIC UNIT MOTOROLA SN54/74LS181 Arora Shalini Guttal Pratibha Modgi Chaitali Shanmugam Ramya Advisor: Dave Parent Date: 05 -11- 05

2. 2 ABSTRACT The SN54/74LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible functions.  Provides 16 Arithmetic Operations  Provides all 16 Logic Operations Operating Clock Frequency = 200MHz Area = (446 X 219)µm Power = 12.26 mW

3. 3 INTRODUCTION Now the current trend in the semiconductor industry is towards high speed and high density.CMOS Technology provides this to support the market needs. In the project, we designed 4 bit ALU using static CMOS technology which  Introduced us to Cadence Software tools.  Taught us design techniques to meet the specification.  Improved our Debugging and testing skill.  Enhanced our team spirit.

4. 4 Design Flow Specification Logic Verification Transistor sizing Spice Simulation Cell based layout Power and Routing Post Extraction

5. 5 Logic Circuit 4-Bit ALU [ Motorola SN54/74LS181 ]  LONG PATH

6. 6 Logic And Arithmetic Function Table

7. 7 Logic Verification in NC Verilog

8. 8 Long Path Sizing: CellWN (µM) WP (µM) Cg (fF) Tphl (ns) Targeted Tphl (ns) Schematic Tphl (ns) Extracted Inv3.355.5595.970.15 0.14 AOI335.858.4245.73110.901 AOI5432 Decomp osed into Nand5, nand4, nand3, nand2, inv. 41.530.90.740.68 EX-OR23.34.3575.460.50.490.46 Nand43.452.434.80.50.490.45 INV2.954.9500.15 0.14 Long Path through logic= 3.2 ns

9. 9 DFF Sizing: Cell WN (µM) WP (µM) Cg (fF) Tphl (ns) Targeted Tphl (ns) Schematic Tphl (ns) Extracted Nand (slave)3.02.55 500.70.690.66 Keeper Mux1.5 Driver Mux5.79.45 Master Nand3.35.4 Keeper Mux1.5 Driver Mux4.659.3 Total time= Time through logic+ Time through DFF Total time: 3.2ns+ 1.4ns=4.6ns

10. 10 Schematic

11. 11 Overall schematic with DFF

12. 12 Layout

13. 13 DRC and Extraction

14. 14 LVS REPORT

15. 15 ALU Test Bench for Logic function

16. 16 Logic output Input A 3 A 2 A 1 A 0 = 1010 B 3 B 2 B 1 B 0 = 1001 M=1 Cn=0 S 3 S 2 S 1 S 0 = 0000 Logic function ¯¯_ =A F 3 F 2 F 1 F 0 = 0101 S 3 S 2 S 1 S 0 = 1111 Logic function =A F 3 F 2 F 1 F 0 = 1010

17. 17 ALU test bench for Arithmetic function

18. 18 Arithmetic function output Input A 3 A 2 A 1 A 0 = 1010 B 3 B 2 B 1 B 0 = 1001 M=0 Cn=1 S 3 S 2 S 1 S 0 = 0000 Arithmetic function =A F 3 F 2 F 1 F 0 = 1010 S 3 S 2 S 1 S 0 = 1111 Arithmetic function = A minus 1 F 3 F 2 F 1 F 0 = 1001

19. 19 Power waveform Power = 61.34 mW / 5 clocks = 12.26 mW

20. 20 Summary Our design met all the specification, speed 263 MHz, area (446 X 219)µm, Power 12.26 mW, Power density 12.55 W/cm 2 We verified all 16 logic and arithmetic functions.

21. 21 Lesson Learned Understand the design flow. Use cell based design. Do DRC and LVS for each cell. Have a rough sketch of the overall floor plan before you layout. Keep track of timing.

22. 22 Thanks to… Prof. Dave Parent for all his help. Cadence Lab and Humming bird software. Classmates for their input. Burger King. AT&T and Cellular services.