1. Sequential Circuits IEP on Synthesis of Digital Design 2007 1 Sequential Circuits S. Sundar Kumar Iyer

2. Sequential Circuits IEP on Synthesis of Digital Design 2007 2 Acknowledgement  Slides taken from http://bwrc.eecs.berkeley.edu/IcBook/index.htm http://bwrc.eecs.berkeley.edu/IcBook/index.htm which is the web-site of “Digital Integrated Circuit – A Design Perspective” by Rabaey, Chandrakasan, Nicolic

3. Sequential Circuits IEP on Synthesis of Digital Design 2007 3 Outline  Background and naming conventions  Timing constraints and stability issues  MUX based latch and registers  Cross-coupled pair  Implementations  Pseudo-static, C 2 MOS, TSPC, …  Pipelining  Schmitt Trigger and Multivibrators

4. Sequential Circuits IEP on Synthesis of Digital Design 2007 4 Sequential Logic 2 storage mechanisms positive feedback charge-based

5. Sequential Circuits IEP on Synthesis of Digital Design 2007 5 Naming Conventions  Rabaey’s Convention  a latch is level sensitive  a register is edge-triggered  There are many different naming conventions  For instance, many books call edge- triggered elements flip-flops  This leads to confusion however

6. Sequential Circuits IEP on Synthesis of Digital Design 2007 6 Latch versus Register  Latch stores data when clock is low D Clk Q D Q  Register stores data when clock rises Clk D D QQ

7. Sequential Circuits IEP on Synthesis of Digital Design 2007 7 Latches

8. Sequential Circuits IEP on Synthesis of Digital Design 2007 8 Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

9. Sequential Circuits IEP on Synthesis of Digital Design 2007 9 Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

10. Sequential Circuits IEP on Synthesis of Digital Design 2007 10 Characterizing Timing Register Latch

11. Sequential Circuits IEP on Synthesis of Digital Design 2007 11 Maximum Clock Frequency Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay t clk-Q + t p,comb + t setup = T

12. Sequential Circuits IEP on Synthesis of Digital Design 2007 12 Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

13. Sequential Circuits IEP on Synthesis of Digital Design 2007 13 Meta-Stability Gain should be larger than 1 in the transition region

14. Sequential Circuits IEP on Synthesis of Digital Design 2007 14 Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

15. Sequential Circuits IEP on Synthesis of Digital Design 2007 15 Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

16. Sequential Circuits IEP on Synthesis of Digital Design 2007 16 Mux-Based Latch

17. Sequential Circuits IEP on Synthesis of Digital Design 2007 17 Mux-Based Latch NMOS onlyNon-overlapping clocks

18. Sequential Circuits IEP on Synthesis of Digital Design 2007 18 Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

19. Sequential Circuits IEP on Synthesis of Digital Design 2007 19 Master-Slave Register Multiplexer-based latch pair

20. Sequential Circuits IEP on Synthesis of Digital Design 2007 20 Clk-Q Delay

21. Sequential Circuits IEP on Synthesis of Digital Design 2007 21 Setup Time

22. Sequential Circuits IEP on Synthesis of Digital Design 2007 22 Reduced Clock Load Master-Slave Register

23. Sequential Circuits IEP on Synthesis of Digital Design 2007 23 Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK Need to use non-overlapping clocks  1 and  2 Must be careful about limiting the non-overlapping period

24. Sequential Circuits IEP on Synthesis of Digital Design 2007 24 Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset

25. Sequential Circuits IEP on Synthesis of Digital Design 2007 25 Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building memory cell

26. Sequential Circuits IEP on Synthesis of Digital Design 2007 26 Sizing Issues Output voltage dependence on transistor width Transient response

27. Sequential Circuits IEP on Synthesis of Digital Design 2007 27 Storage Mechanisms D CLK Q Dynamic (charge-based) Static

28. Sequential Circuits IEP on Synthesis of Digital Design 2007 28 Making a Dynamic Latch Pseudo-Static

29. Sequential Circuits IEP on Synthesis of Digital Design 2007 29 Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static Clocked CMOS

30. Sequential Circuits IEP on Synthesis of Digital Design 2007 30 Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap May have dual edge registers

31. Sequential Circuits IEP on Synthesis of Digital Design 2007 31 Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) True Single Phase Clocked Registers (avoids CLK’)

32. Sequential Circuits IEP on Synthesis of Digital Design 2007 32 Including Logic in TSPC AND latch Example: logic inside the latch

33. Sequential Circuits IEP on Synthesis of Digital Design 2007 33 TSPC Register

34. Sequential Circuits IEP on Synthesis of Digital Design 2007 34 Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell:

35. Sequential Circuits IEP on Synthesis of Digital Design 2007 35 Pulsed Latches

36. Sequential Circuits IEP on Synthesis of Digital Design 2007 36 Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

37. Sequential Circuits IEP on Synthesis of Digital Design 2007 37 Hybrid Latch-FF Timing

38. Sequential Circuits IEP on Synthesis of Digital Design 2007 38 Pipelining Reference Pipelined

39. Sequential Circuits IEP on Synthesis of Digital Design 2007 39 Latch-Based Pipeline

40. Sequential Circuits IEP on Synthesis of Digital Design 2007 40 Non-Bistable Sequential Circuits─ Schmitt Trigger VTC with hysteresis Restores signal slopes

41. Sequential Circuits IEP on Synthesis of Digital Design 2007 41 Noise Suppression using Schmitt Trigger

42. Sequential Circuits IEP on Synthesis of Digital Design 2007 42 CMOS Schmitt Trigger Moves switching threshold of the first inverter

43. Sequential Circuits IEP on Synthesis of Digital Design 2007 43 Schmitt Trigger Simulated VTC 2.5 V X (V) V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the PMOS deviceM 4. The width isk* 0.5 m. m 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 V x (V) k = 2 k = 3 k = 4 k = 1 V in (V) 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5

44. Sequential Circuits IEP on Synthesis of Digital Design 2007 44 CMOS Schmitt Trigger (2)

45. Sequential Circuits IEP on Synthesis of Digital Design 2007 45 Multivibrator Circuits

46. Sequential Circuits IEP on Synthesis of Digital Design 2007 46 Transition-Triggered Monostable

47. Sequential Circuits IEP on Synthesis of Digital Design 2007 47 Astable Multivibrators (Oscillators) 012N-1 Ring Oscillator simulated response of 5-stage oscillator

48. Sequential Circuits IEP on Synthesis of Digital Design 2007 48 Differential Delay Element and VCO in 2 two stage VCO v 1 v 2 v 3 v 4 V ctrl V o 2 V o 1 in 1 delay cell simulated waveforms of 2-stage VCO