1. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2 Mother Board Design Status Exogam Collaboration Abderrahman BOUJRAD GANIL France

2. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad EXOGAM2  Agenda  NUMEXO2_P1  Design goals  Status  NUMEXO2_P2  Introduction  Block diagrams  Status

3. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P1-Design Goals  Early prototype: NUMEXO2 Phase 1  a simple digitizer (14 bits /100MHz) without GTS  The design goals were essentially three fold :  Validation of the critical components, particularly the FADC Ads6244  Validation of the PowerPC architecture for Slow Control and data readout flow  Testing and validation of the analysis tools developed by the GAP (Groupe d’Acquisition pour la Physique)

4. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P1 The NIM digitizer prototype (phase1)

5. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P1 - Status  Better Knowledge on PowerPC Architecture & Embedded Linux  Peripherals: SRAM, SDRAM, Flash, SPI, UART, Ethernet  Conversion chain (14b / 100 MHz & 200 MHz)  validated  14b / 100 Mhz, NUMEXO2_P1  14b / 200Mhz, ML605 Xilinx Evaluation Kit  for NEDA  Vigru (Analysis tools)  validated   Energy Algorithms (MWD) & trigger concept  validated  Knowledge on high speed serial links  validated

6. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2-Introduction NUMEXO2 Phase 2 (NUMEXO2_P2) : full digitizer & GTS implementation  16 Channels digital conversion system  Mezzanine card concept  more flexibility  Up to 16 Triggers,Time Stamping and Clock tree  PCI Express (4x) for NEDA and ADONIS  High counting rate ( 50 to 100 KHz)

7. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2-Introduction  NUMEXO2 phase 2 started on February 24, 2011  The Architecture is now completely defined  CAD was shared between the different contributors :  GANIL, IPNO, IFJPAN  Firmware developments :  PCIexpress, IP_oscilloscope  IPNO / Orsay  ADC_Interface_IP  HIL / Warsaw  Gts_leaf_IP  IFJPAN / krakow

8. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2- Bloc Diagram ADC Logic -FADC samples collection -Digital Processing -Trigger -Data formatting -Inspection control PPC Common Logic GTSFanin ADC Logic Interface Clocks (Local & Recovered) Delay Line Optical Link Flash (Linux) PROM (VHDL) PROM (VHDL) Ethernet Gigabit PCIe (4 Lane) DACs (Test, control, inspection) Serial link DDR2 Mux 4 2*FADC 14 bits 200MHz FIFO -------- RAW DATA (event parameters) Samples

9. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 Virtex5 Block diagram IFJPAN krakow IUAC New Delhi GANIL Caen IPNO Orsay HIL Warsaw

10. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 assignment of Virtex5 banks PCIe GTS Iserdes Parallel data GTS FIFO_PCIe GTS Preliminary

11. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 Virtex6 Block diagram GANIL Caen IPNO Orsay

12. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 assignment of Virtex6 banks

13. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2-Firmware Status  The architecture is approved  Elements such as the DDR2, the flash, Ethernet, PCI Express 8X (developed by IPNO), the serial bus (RS232, SPI and IIC) and the serial link for data recovery for NEDA and ADONIS were implemented in the PPC440 architecture  It remains the implementation of GTS and data readout on V5:  GTS IPs (Global Trigger Systems, Dulny & Czermak / IFJPAN)  Clock recovery IP developed by ET (IUAC)  Data readout IP (Radeck, HIL)

14. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 - CAD Status  90 % of CAD is done but need to be verified :  The embedded Linux CAD (DDR2,Flash, ethernet…) associated to the PPC 440 is done  GANIL  The CAD for the GTS features  GANIL & IFJPAN  The CAD associated to the Virtex6 and its peripherals is done  GANIL  CAD of PCI Express and its peripherals  IPNO  CAD of power management almost finished  GANIL

15. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad Principal IPs => validated on numexo2_P1 & on the Xilinx ML605 evaluation kit RTL view from SYNPLIFY PRO synthesis tool ISERDES EnergyEmbedded Histogram NUMEXO2_P2 V6 Firmware

16. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 – Energy visualisation  = 1.3 1 LSB = 0.802 mV Embedded logic analyser

17. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad EXOGAM clover CM2DM signal box ADS62P49@250MHz ML605 Co60 source spectrum FWHM = 2.7 keV @ 1.3 MeV CSP output MWD output FADC 14 bits @ 250MHz + MWD NUMEXO2_P2 - Co60 spectrum

18. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2-Digital TDC TEST BENCH

19. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2 - Digital TDC Resolution obtained with the vernier alone without the DFC

20. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2- Front and Back sides FRONT SIDE BACK SIDE

21. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad FRONT SIDE BACK SIDE NUMEXO2_P2- mother card Implementation The implementation of the components on the motherboard is in progress

22. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad NUMEXO2_P2- mezzanine card positions

23. Prometeo Workshop (Valencia) November 17-18, 2011 A. Boujrad  Thank you for your attention