DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time.

DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time System Design Considerations 3.Hardware Interrupts (HWI) 4.Software Interrupts (SWI) 5.Task Authoring (TSK) 6.Data Streaming (SIO) 7.Multi-Threading (CLK, PRD) 8.BIOS Instrumentation (LOG, STS, SYS, TRC) 9.Static Systems (GCONF, TCONF) 10.Cache (BCACHE) 11.Dynamic Systems (MEM, BUF) 12.Flash Programming (HexAIS, Flashburn) 13.Inter-Thread Communication (MSGQ,...) 14.DSP Algorithm Standard (XDAIS) 15.Input Output Mini-Drivers (IOM) 16.Direct Memory Access (DMA) 17.Review

Learning Objectives  Describe the concepts of foreground / background processing  List details of the Idle (IDL) thread  Compare Hardware Interrupts (HWI) to ISR’s  Demonstrate how to invoke Interrupt Preemption  Describe the purpose of the Interrupt Monitor  Create an HWI object using CCS Gconf tool  Add an idle thread to a given CCS project  Observe performance of threads using CCS T TO Technical Training Organization 2

Hardware Interrupts  Concepts  Idle (IDL)  Hardware Interrupts (HWI)  Interrupt Preemption  Interrupt Monitor  Lab Foreground (HWI) Background (IDL) T TO Technical Training Organization 3

Foreground / Background Scheduling main() { init while(1) nonRT }  IDL events run in sequence when no HWIs are posted  HWI is ISR with automatic vector table generation  Any HWI preempts IDL, HWI may preempt other HWI if desired  If multiple HWI are present in IDL, control passes to highest priority HWI ISR get buffer process printf() main() { init return } BIOS Scheduler HWI get buffer process LOG_printf() IDL nonRT + instrumentation T TO Technical Training Organization 4

Foreground / Background HWI Highest Priority Lowest Priority Process Sample Background Background scheduler allows you to defer less urgent processes from hardware interrupt service routines to the background T TO Technical Training Organization 5

Interrupt Enable Management Concepts  Interrupt response is managed by a 2 level enable system:  Global Interrupt Enable (GIE) bit – indicates if any interrupts will be taken  Interrupt Enable (IE) register – indicates which interrupts are of interest  Pending interrupt signals are maintained in an Interrupt Flag (IF) register until responded to, and are automatically cleared when serviced  On reset, GIE and all IE bits are cleared  In main() whichever interrupts are desired initially should be enabled by ORing 1s to their corresponding bit position(s) in the IE  When main() exits, GIE is automatically enabled as part of the start of the BIOS scheduler environment  When an HWI is recognized: IF bit & GIE are cleared. GIE is cleared to avoid preemption amongst HWI. On return from the HWI, GIE status is restored  Using the dispatcher on an HWI allows re-enable of GIE within the HWI if preemption is desired. Dispatcher also allows the selection of which other HWIs will be able to preempt the given HWI 1 0 1 0 0 1 0 1 0 1 1 1 1 IF IE GIE Interrupt Sources Event! pGIE = GIE IF n = GIE = 0 stack = PC PC = vector b HWI context save HWI runs {... } context restore GIE = pGIE PC = prior PC T TO Technical Training Organization 6 ICR ISR

Interrupt Management - Additional Info T TO Technical Training Organization  ICR for manually clearing a flag bit  ISR for setting one  There are BIOS API for handling these, as well as setting the IER  C64x+ has an additional interrupt error event which can be used to indicate a missed interrupt  If a flag is set, and another comes in, an error event is generated  This event can be mapped into a different (higher priority) interrupt or into an exception/nmi 7

Idle  IDL  Lowest priority - soft real-time - no deadline  Idle functions executes sequentially  Priority at which real-time analysis is passed to host  Likely IDL Activities  Low power systems - idle the processor  Systems in test - instrumentation  User interfaces  Defragmentation  Garbage collection Return from main( ) InactiveReadyRunning Started Resume Preempted T TO Technical Training Organization 9

Creating a New Idle Object Via GCONF 1/4 Creating a new Idl Obj 1. right click on IDL mgr 2. select “Insert IDL” T TO Technical Training Organization 10

Creating a new Idl Obj 1. right click on IDL mgr 2. select “insert IDL” Creating a New Idle Object Via GCONF 2/4 Creating a new Idl Obj 1. right click on IDL mgr 2. select “Insert IDL” 3. type object name T TO Technical Training Organization 11

Creating a New Idle Object Via GCONF 3/4 T TO Technical Training Organization Creating a new Idl Obj 1. right click on IDL mgr 2. select “Insert IDL” 3. type object name 4. right click on new IDL 5. select “Properties” 12

Creating a new Idl Obj 1. right click on IDL mgr 2. select “insert IDL” 3. right click on new IDL 4. select “rename” 5. type new name 6. right click on new IDL 7. select “properties” Creating a New Idle Object Via GCONF 4/4 Creating a new Idl Obj 1. right click on IDL mgr 2. select “Insert IDL” 3. type object name 4. right click on new IDL 5. select “Properties” 6. indicate desired User Comment (FYI) Function to run in IDL Whether to include this function in the CPU load display T TO Technical Training Organization 13

Hardware Interrupts  Much like “ISR”s (interrupt service routines)  Vector table automatically rendered  Add interrupt keyword in front of function declaration  Context switch (save/restore of state of CPU around the HWI on the system stack) automatically performed when interrupt keyword is used  Are a priority foreground activity that preempt background activity  HWIs are taken in order of priority  Default is one HWI does not preempt another: when a running HWI returns, then execution will pass to the highest priority HWI then available (or back to IDL if no HWI are flagged) Foreground Background T TO Technical Training Organization 15

HWI_c (p4) HWI_a (p6) IDL HWI_b (p5) HWI Scheduling Example Highest Priority Lowest Priority Legend Running Ready  Any HWI will preempt IDL  Standard practice is that no HWIs preempt any other running HWI  On return from an HWI, control is passed to highest pending HWI  Is it always desirable to make high priority HWIs wait for lower priority HWIs to conclude before they are serviced? time 1 1 1 2 2 2 1212 Context Save Context Restore T TO Technical Training Organization 16

Creating a New HWI Object Via GCONF 1/2 Creating a new HWI Obj 3. select “Properties” 1. expand the HWI mgr T TO Technical Training Organization 2. right click on desired HWI 17

Creating a New HWI Object Via GCONF 2/2 4. select interrupt source and function to run T TO Technical Training Organization Creating a new HWI Obj 1. expand the HWI mgr 2. right click on desired HWI 3. select “Properties” 18

Adding Preemption to HWIs  When preemption amongst HWIs is desired, default HWI scheduling can be manually overriden  Developer can use the dispatcher in CCS to make any desired HWI preemptible  Preemption can be on all higher numbered HWIs, or on any selected group of higher or lower HWI  Adding the dispatcher increases context save and restore effort, some extra system overhead incurred  Use of the dispatcher requires removing the interrupt keyword in the function declaration  While seemingly desirable, HWI preemption will be seen to be only one of several scheduling options - handy in some cases, unneeded in others T TO Technical Training Organization 20

HWI_c (p4) HWI_a (p6) IDL HWI_b (p5) Preemptive HWI Scheduling Example Running Ready Legend  Any HWI will preempt IDL  HWI priority 3 does not preempt HWI priority 2  HWI priority 1 preempts HWI priority 2  note : if the dispatcher had been differently configured, HWI_a could have as easily preempted HWI_b, and HWI_c not so allowed time Highest Priority Lowest Priority T TO Technical Training Organization 21

Enabling Preemption via the Dispatcher  Right click on an HWI and select the “properties” option  Select the Dispatcher tab in the properties dialog box  Check the Use Dispatcher box  Select HWIs that will preempt this HWI via the Interrupt mask  Option: Arg field allows an argument to be passed to the HWI  Be sure to remove ‘interrupt’ keyword in front of ISR when using dispatcher ! ! To activate the dispatcher for a particular HWI: T TO Technical Training Organization 22

Assembly Code Dispatch Option myISR: HWI_enter ABMASK, CMASK, IEMASK, CCMASK... SWI_post(&mySwi);... HWI_exit ABMASK CMASK IERRESTOREMASK CCMASK  HWI_enter() and HWI_exit() are assembly macros  Use _enter at the start of an HWI and _exit at the end of the HWI  Allows BIOS calls to be correctly invoked between the functions  User specifies preemption by other HWIs (IEMASK)  GIE enabled on _enter and restored on _exit  User specifies registers to save/restore (ABMASK, CMASK)  User specifies cache control options (CCMASK)  Cannot be used on HWIs that employ the BIOS dispatcher!  Do not use interrupt keyword when using _enter and _exit !  Usually use BIOS dispatcher, for final optimization consider _enter, _exit stack A1 A2... CPU A1 A2... Interrupt preemption enabled here T TO Technical Training Organization 23

Comparison of Interrupt Options Ease of useEasy Demanding Post to scheduler ? YesNOYes Chance of errorLowMediumHigh SpeedMediumFastCan be fastest Code sizeSmaller Larger BIOS DispatcherInterrupt Keyword HWI_enter, HWI_exit  Recommended: Use the BIOS dispatcher as a first choice  Allows for selectable nesting of interrupts and BIOS scheduler calls  Easy to set up and manage via the config tool  Use HWI_enter and HWI_exit to optimize extremely speed critical HWI  Can specify which registers to save, cache details, etc  Still allows BIOS calls and preemption  Requires knowing which registers to save for the given HWI  Interrupt keyword allows fast and small HWI – but no BIOS kernel API  Any calls of BIOS API that prompt kernel scheduler action are prohibited  Nesting of HWI requires manual management of GIE and IER ONLY CHOOSE ONE OF THE ABOVE OPTIONS PER HWI T TO Technical Training Organization 24

HWI API Summary HWI_enterTell BIOS an HWI is running, GIE enabled HWI_exitTell BIOS HWI about to exit HWI_enableTurns on GIE bit, enables ISRs to run HWI_disableSets GIE to 0, returns prior GIE state HWI_restoreRestor GIE to given state before HWI_disable HWI APIDescription HWI_dispatchPlug Write a fetch packet into the vector table – dynamic ISR creation Mod 7 T TO Technical Training Organization 25 Interrupt management intrinsics: Faster than the BIOS API Unsigned int_disable_interrupts(); Unsigned int_enable_interrupts(); Void_restore_interrupts(unsigned int);

HWI Monitor Option If monitor is other than “nothing”:  Stub function ‘plugged’ into vector table by DSP/BIOS  In turn, this will call your ISR Note: stubs are also used when the dispatcher is invoked default configuration vector table br isr 0 1. n. isr 0 1 n monitoring isr1 vector table br isr 0. n. isr 0 n br stub 1 isr 1 stub 1 T TO Technical Training Organization 27

Setup of HWI Monitor Option 1/2 T TO Technical Training Organization  Right click on an HWI; select “properties”  Select the General tab in the dialog box  Under “monitor” select parameter to observe To activate the monitor option for an HWI: 28

Setup of HWI Monitor Option 2/2  Right click on an HWI; select “properties”  Select the General tab in the dialog box  Under “monitor” select parameter to observe  For ‘data value’, select its address / label  Identify type (signed / unsigned) of datum  Select STS function - covered later... T TO Technical Training Organization To activate the monitor option for an HWI: 29

HWI Object  HWI objects are pre-defined; you can assign properties with the configuration tool  DSP/BIOS automatically sets up interrupt vectors  Diagram is conceptual - not literal - object format interrupt source function monitor addr type operation your ISR pin, timer, etc. Allows you to monitor a variable or register for every ISR Implemented with DSP/BIOS statistics object address (label) of data value signed, unsigned data value, nothing, SP, top of SW stack, register STS_add (+, -, abs) STS_delta (+, -, abs) covered later T TO Technical Training Organization 30

FIR Filter Overview - 30 29 28... 1 0  Read new data from ADC i-31A/DSP 31  Store to top of delay line T TO Technical Training Organization 32

c0 c1 c2 c3... c30 c31 xxxxxxxxxxxx +++++=+++++= FIR Filter Overview - 30 29 28... 1 0  Read new data from ADC i-31A/DSP y(31) = c0*x(31) + c1*x(30) + c2*x(29) +... + c30*x(1) + c31*x(0)  Send results to DAC  Convolve with coefficients 31  Store to top of delay line D/A out31 SP T TO Technical Training Organization 33

c0 c1 c2 c3... c30 c31 xxxxxxxxxxxx +++++=+++++= FIR Filter Overview - 30 29 28... 1 0  Read new data from ADC i n31 A/DSP D/A out31 SP y(31) = c0*x(31) + c1*x(30) + c2*x(29) +... + c30*x(1) + c31*x(0)  Manage delay line  Send results to DAC  Convolve with coefficients 31  Store to top of delay line - 31 30 29... 2 1 y(32) = c0*x(32) + c1*x(31) + c2*x(30) +... + c30*x(2) + c31*x(1)... y(n) = c0*x(n) + c1*x(n-1) + c2*x(n-2) +... + c30*x(n-30) + c31*x(n-31) T TO Technical Training Organization 34

Audio Output (48 KHz) Lab 3: Hardware Interrupt - HWI ADC AIC33 Audio Input (48 KHz) McBSP DRR FIR.c FIR Code DAC AIC33 McBSP DXR isrAudio hist[0]=MCBSP_DRR if( sw0 == 1 ) dataOut=FIR(hist...) for (i = N-1; i >= 0; i--) hist[i+1] = hist[i]; else {dataOut=hist[0]} MCBSP_DXR = dataOut mcbsp.c coeffs.c Coefficients BIOS\Labs\HWBIOS\Labs\Work BIOS\Labs\Algos  Create a new project, define build options  Add the components noted below  Set up a BIOS configuration, define the HWI  Build the project, download and debug on the EVM  Add an IDL object to monitor 2 EVM DIP switches T TO Technical Training Organization 35

void isrAudio(void) { static short i; // loop index static int dataIn, dataOut; // interface to MCBSP read/write static short dataOutL, dataOutR; // FIR results of L & R channels dataIn = MCBSP1_DRR_32BIT; // Get one stereo sample (L & R Data) buf[0] = (short)dataIn; // Place Left data sample in delay line buf[1] = (short)(dataIn >> 16); // Put Right data sample in delay line for (i = FIRSZ-2; i >= 0; i--) // for 2*(#coeffs-1) buf[i+2] = buf[i]; // move all data down 1 pair if( sw0 == 1 ) { // If filtering is on... fir(&buf[0], &coeffs[sw1][0], &dataOutL, FIRSZ, 1); // left channel FIR fir(&buf[1], &coeffs[sw1][0], &dataOutR, FIRSZ, 1); // right channel FIR dataOut = 0x0000FFFF & dataOutL; // get left value for output dataOut |= 0xFFFF0000 & (dataOutR << 16); // or in right chan in MSBs } else // if filtering is 'off'... dataOut = dataIn; // new input copied to output MCBSP1_DXR_32BIT = dataOut; // Send data to codec, (single channel) } FIR.c in \Algos mcbsp.c in \HW mcbsp.c in \HW audio.c : HWI Function Encapsulation 36

included headers global variables main() - init arrays - init HW - enable Int HWI - read A/D - if ‘on’, call FIR - else ‘out’ = ‘in’ - write D/A #include"myWorkcfg.h"// FIRST: config file header #include"codec.h"// serial port code access #include"coeffs.h"// fir filter coeff access #include"dipMonitor.h"// DIP init and reader access #include // allows access to EVM init fxn #defineFIRSZ64 void isrAudio(void); void fir(short data[ ], short coeff[ ], short result[ ], int firsz, int bufsz); short sw0 = 0;// controls run/bypass of FIRs shortsw1 = 0;// low pass vs high pass filter short buf[2*FIRSZ];// interlaced stereo data buffr externcregister volatile unsigned intCSR;// control status register externcregister volatile unsigned intICR;// interrupt clear register externcregister volatile unsigned intIER;// interrupt enable reg. // ========= MAIN - init and return to begin BIOS Scheduler environment...===== void main(void){ short i;// loop counter EVMDM6437_init();// init EVM6437 HW initCodec();// init McBSP1; s/u AIC via I2C initDipSwitches();// init the DIP switch reader for (i = 0; i < 2*FIRSZ; i++) // for size of stereo buffer buf[i] = 0;// clear delay line ICR = 0x10;// clear INT4 (precaution) IER |= 0x10;// enable INT4 as CPU interrupt MCBSP1_SPCR = 0x00010001;// start McBSP } // ===== isrAudio() - Serial Port Interrupt Service Routine: BIOS HWI ======== void isrAudio(void) { static shorti;// loop counter static int dataIn, dataOut;// i/f to MCBSP read/write static shortdataOutL, dataOutR;// FIR results of L & R channels dataIn = MCBSP1_DRR_32BIT; // get one stereo sample (L & R Data) buf[0] = (short)dataIn;// put Left data sample in delay line buf[1] = (short)(dataIn >> 16); // put Right data sample in delay line for (i = FIRSZ-2; i >= 0; i--) // for 2*(#coeffs-1) buf[i+2] = buf[i];// move all data down 1 pair if( sw0 == 1 ){ // if SW0 is down... fir(&buf[0], &coeffs[sw1][0], &dataOutL, FIRSZ, 1); // FIR: 1 sample L fir(&buf[1], &coeffs[sw1][0], &dataOutR, FIRSZ, 1); // FIR: 1 sample R dataOut = 0x0000FFFF & dataOutL;// left result is 16 LSBs dataOut |= 0xFFFF0000 & (dataOutR << 16); // right result is 16 MSBs } else // if filtering is 'off'... dataOut = dataIn;// new input copied to output MCBSP1_DXR_32BIT = dataOut;// output 1 stereo result to codec } 38 function prototypes

Working with TCF Files  Create a new TCF file based on the DM6437 ‘seed’ file  Define an HWI on Int12 that calls the isrAudio() function  Add an IDL object that calls the readDipSwitches() function T TO Technical Training Organization 37

Hardware Interrupts  Concepts  Idle (IDL)  Hardware Interrupts (HWI)  Interrupt Preemption  Interrupt Monitor  Lab  optional information Foreground (HWI) Background (IDL) T TO Technical Training Organization 39

Lab Details FilterDebugRelease Off4.6%1.4% On68%3.9% These are the results I got running labs 3C and 3D. Yours may not be exact, but they should be close. Key points to make – with the filter off, load is low since no math is being done filter on – load is VERY high unoptimized optimization is a BIG help to performance – and is easy

ti Technical Training Organization 47

C62/C64 API The C62 and C64 modules provide certain target-specific functions and definitions for the TMS320C6000 family of processors. ❏ C64_disableIER : disables interrupts by clearing the bits specified by mask in the IER. Returns bits cleared. This value should be passed to C64_enableIER to re-enable masked interrupts oldmask = C64_disableIER(mask); // mask = C64_EINTxx where xx=int. # ❏ C64_enableIER. ASM macro to enable selected interrupts in IER C62_enableIER(oldmask); ❏ C64_plug. Plug interrupt vector C64_plug(vecid, fxn, dmachan);

HWI API ❏ HWI_dispatchPlug. Plug the HWI dispatcher HWI_dispatchPlug(vecid, fxn, dmachan, attrs); ❏ HWI_eventMap. Assign interrupt source number to an HWI object. HWI_eventMap(vectID, eventID); ❏ HWI_isHWI. Check current thread calling context. typedef struct HWI_Attrs { Uns intrMask; /* IER bitmask, 1="self" (default) */ Uns ccMask /* CSR CC bitmask, 1="leave alone" */ Arg arg; /* fxn arg (default = 0)*/ } HWI_Attrs; DSP/BIOS supports the C64x+ interrupt selector through the HWI Module. You can route one of the 128 system events to a specific HWI object by specifying the event number as the "interrupt selection number“ in the HWI Object Properties. This one-to-one mapping supports up to 12 maskable interrupts. The C64x+ event combiner is supported by the ECM Module. If the 16 HWI objects are sufficient for the number of HWI functions your application needs to run, you need not enable the ECM module. You do not need to know whether your C function will be run by the HWI module or ECM module when you write the function. (The ECM module uses the HWI dispatcher, and so its functions cannot be completely written in assembly.)

ECM API ❏ ECM_disableEvent. Disable the specified event at run-time. ❏ ECM_dispatch. Handle events from the event combiner. ❏ ECM_dispatchPlug. Create an ECM dispatcher table entry. ECM_dispatchPlug(eventId, fxn, *attrs); ❏ ECM_enableEvent. Enable the specified event at run-time.

DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time.

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DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time.

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Presentation on theme: "DSP/BIOS System Integration Workshop Copyright © 2004 Texas Instruments. All rights reserved. T TO Technical Training Organization 1 1.Introduction 2.Real-Time."— Presentation transcript:

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