1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design Jacob Maxa Results of Phase 4: Chip Layout 10.01.2013 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Challenge Create a fully working chip layout Redo the same task with additional I/O pads Ideas Optimize VHDL/Verilog source and netlist Shrink internal bit width from 10 to 8 Minimize needed core area Rectangular layout Shorten wires as good as possible (high effort routing) Create a special clock mesh H-Tree form GND guard shield to avoid crosstalk Optimize for DFM Antenna fixing

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Routing Global Routing Generate global routing mesh Detail Route Connect pins with it corresponds and the global mesh Post Route Optimization Fix violated design rules Via – combine/split vias to fit DRC Wire – shorten wires Fix Antenna Timing Driven Optimize to low wire delay SI (signal integrity) Driven

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Clock Mesh After cell placement Uses clock buffer Fill free spaces between cells H-Tree from Double sided shield with GND net M3 & M4 Slide 4

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Timings Adding timing constraints to improve optimizations Repeat for highest frequency Perform design optimization Reroute wires Density: 90.799% Slide 5 +--------------------+---------+---------+---------+---------+---------+---------+ | Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | +--------------------+---------+---------+---------+---------+---------+---------+ | WNS (ns):| 0.010 | 0.048 | 0.010 | N/A | N/A | N/A | | TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A | | Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A | | All Paths:| 296 | 141 | 155 | N/A | N/A | N/A | +--------------------+---------+---------+---------+---------+---------+---------+ | Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | +--------------------+---------+---------+---------+---------+---------+---------+ | WNS (ns):| 0.047 | 0.047 | 1.644 | N/A | N/A | N/A | | TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A | | Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A | | All Paths:| 296 | 141 | 155 | N/A | N/A | N/A | +--------------------+---------+---------+---------+---------+---------+---------+

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results (1/3) Slide 6 Mandatory values for FGPAMandatory values for ASIC Phase1234 UnitSynthesisBackannotationUnitST65 (Netlist)ST65 (Layout) Frequency f MHz365,23318,066MHz250,98565 Area A # LUT-FF pair 233182μm 2 3594,75993269,448 # Pipeline Stages 133133 Metric MHz/# LUT- FF pair 1,56751,7476 J -2 = W -2 s -2 = s 4 /(kg 2 m 4 ) 5,4253*10 27 1,73663*10 26

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results (2/3) Slide 7 ASIC Layout Values UnitValue Timing (T min / f Max )ps / MHz1769,9 / 587 Power (P dyn / P leak )µW / nW1,8978 / 968,5890 # Pipeline Stages13 Benchmark/MetricJ -2 1,73663*10 26 Core Sizeµm 2 3269,448 Core Utilization190,799 Power requirements 22,38 % clock network 57,64 % registers 19,98 % combinational

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Results (3/3) Before Optimization After Optimization

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Layout with Pads ASIC Layout Pads Values UnitValue Timing (T min / f Max )ps / MHz1769,9 / 565 Power(P dyn / P leak )mW / mW65,780/ 6,2666 # Pipeline Stages13 Benchmark/MetricJ -2 7,74405*10 20 Core Sizeµm 2 248375,4102 Core Utilization191,388 Power requirements 99,29 % I/O Pads 0,14 % clock network 0,45 % registers 0,12 % combinational

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock End Thanks for your attention! Questions? Slide 10

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Metric Slide 11