1. AR3BL2 Measurements at Penn 3 rd Assembled board November 9 04 FMN

2. 3BL2 with/without 10pF Load Clock Min - Max 300KHz Rate

3. 3BL2 Test Pulse Scan Shaping Controll 0,0 and 1,1 Test Pulse not functional in this location #46 even after replacement of DTMROC. Board layout appears OK using DVM and examining Gerbers. All 3BL2, 1 locations OK for even and Odd test pulse lines.

4. Data Read Tests Delay from First L1A 1.0us and 3.18uS ( “in time”)

5. 3BL2 Data Read Noise Antenna @#46 Data Out to @#47 Load Board “ In time ” Delay from First L1A 3.18uS

6. 3BL2 Measurement Summary Threshold scans OK. Clock, Data pickup very low. A dditional Tests Performed DLL lock at 2.4V All locations locked. Voltage /Temp Readout - all locations as expexted. BX / DX delay scans look reasonable. ?? Location @#46 test pulse ?? High Threshold --- not done yet