1. CSE241 Formal Verification.1Cichy, UCSD ©2003 CSE241A VLSI Digital Circuits Winter 2003 Recitation 6: Formal Verification

2. CSE241 Formal Verification.2Cichy, UCSD ©2003 Formal Verification - Definition  Formal verification: l Logic equivalence checking l It verifies the logical equivalence of RTL, gate or transistor level netlists to each other. l Does not guarantee that the initial design met the design specification -Ignores timing information -Only boolean equivalence

3. CSE241 Formal Verification.3Cichy, UCSD ©2003 Formal Verification Advantages  Does not test functional correctness l No input vector creation necessary l No test vectors for logical function  Faster verification cycle for the design!  Only generates functional vectors for simulation to identify the bugs

4. CSE241 Formal Verification.4Cichy, UCSD ©2003 Technology Libraries  Verifies logic function independent of technology and timing  There is no timing check l Timing issues must be checked by static timing analysis or dynamic timing simulation.  Can compare different technology and different hierarchical structure. Artisan 0.13Artisan 0.18 Clock Period = 2.5 nsClock Period = 5 ns

5. CSE241 Formal Verification.5Cichy, UCSD ©2003 Formal Verification Application  Verifies equivalence of design at different stages of the ASIC flow  Makes sure that no logical changes are made RTL Logically Equivalent? RTL Modification Synthesized Correctly? Synthesized Gate Level netlist CTS, Repeater, P&R, & Optimization correctly? P & R netlist Logic Equivalence Checker

6. CSE241 Formal Verification.6Cichy, UCSD ©2003 Formal Verification - Flow  Equivalence checking is a branch of static verification l Employs formal, mathematical techniques l Proves two versions of a design are, or are not, functionally equivalent l EC flow consists of four primary stages: -Read -Match -Verification -Debug  Match and verification stages are those most impacted by design transformations

7. CSE241 Formal Verification.7Cichy, UCSD ©2003 Read  Read: l 1.During the read stage, both versions of the design are read into the EC tool l 2. Segmented into manageable sections called logic cones -Logic cones (Figure 1) are groups of logic bordered by registers, ports, or black boxes. The output border of a logic cone is referred to as the compare point. Diagram Courtesy of Synopsys

8. CSE241 Formal Verification.8Cichy, UCSD ©2003 Match  Match: l During the match phase, tools attempt to match, or map, compare points l Reference (golden) design is used for comparison  Types of comparisons: l Non-function (name-based) l Function-based matching methods l Best performance is by the more efficient name-based methods

9. CSE241 Formal Verification.9Cichy, UCSD ©2003 Compare Points – Logic Cones Diagram Courtesy of Synopsys

10. CSE241 Formal Verification.10Cichy, UCSD ©2003 Verification Comparison Types  RTL to RTL Verification  Gated clocks addition  Critical path optimization  Other RTL to gate constraints  RTL to Gate Verification  Post synthesis of an HDL design  Gate to Gate Verification  Buffer insertion for re-timing  P&R buffers  Test logic  Clock trees  Scan chains

11. CSE241 Formal Verification.11Cichy, UCSD ©2003 Formal Proof Issues  Formal tools are great at proving that one logic cone is equivalent to another l Problem: matching up the cones in one input file with the cones in the other input file. l If you can't figure out which cones are supposed to be equivalent, then the tool can't help you  Normally done by matching up the signal names l Done automatically l Some tools alter signal names. l Change the borders of cones -No direct equivalence between cones in one file and the other -Causes formal tool to do tedious process of matching up cones based on the topology of the network -Very time-consuming

12. CSE241 Formal Verification.12Cichy, UCSD ©2003 Types of Input  Formality, Formal Pro and others use l.db, l Verilog, VHDL l Spice l Edif  Functional descriptions of library cells: l Used for mapping the designs into generic models  RTL and the gate level design netlists: l Are converted into generic models at the mapping stag

13. CSE241 Formal Verification.13Cichy, UCSD ©2003 Mapping Methods  Name based mapping for design with mostly same names.  No name mapping for designs with mostly different names.  Extra points that exist in one design but not in other are not mapped.

14. CSE241 Formal Verification.14Cichy, UCSD ©2003 Generic Tool Function - Diagnosis  Locate the error pattern l What is the cause of the mismatch? l List the possible sources of the mismatch -All paths and probable mismatch points l Report gates to trace the fan-in or fan-out of the mismatch points -Check for gated designs