1. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 1 Timing and Event System for the LCLS Electron Accelerator* * See Remi Machet and Steve Lewis for LCLS photon event system plans.

2. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 2 Outline Introduction Architecture and Pictures Issues and Tasks

3. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 3 LCLS Introduction The Linac Coherent Light Source is an X-ray FEL based on the SLAC Linac: 1.0nC, 14GeV e - are passed thru an undulator, a Self Amplifying Stimulated Emission process produces 1.5 Angstrom X-Rays. LCLS is an addition to the existing SLAC Linac: it uses the last 1/3 of the machine ► This is important to note because we have to integrate the New LCLS Timing System with the Existing Linac (SLC) Timing System.

4. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 4 (pre-LCLS) SLAC Accelerator Complex ( Lots of Pieces)

5. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 5 Existing SLAC Timing System The Linac is a Pulsed Machine (get a packet of beam per pulse) runs at a max of 360Hz (120Hz) Three Main Timing Signals: 476MHz Master Accelerator Clock (runs down 2mile Heliax Main Drive Line cable) 360Hz Fiducial Trigger (used to ‘tell’ devices when the beam bunch is present) / encoded onto the 476MHz master clock 128-Bit PNET (Pattern Network) Digital Broadcast (contains trigger setup, beam type & rate information) Existing system used for RF modulator triggers.

6. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 6 LCLS Timing System Old CAMAC System is no longer viable for new Systems (performance limited, obsolete) Seek to implement a new Timing System that has similar functionality, better performance, and can be laid atop the old system, working alongside it In addition, LCLS has its own master oscillator (PLL sync’d with Linac MO) and local phase reference distribution system at S20 ►LCLS Electron Accelerator is VME based (most CPUs are MVME6100), using High-Speed digital serial links to send Clock, Trigger and Data all on one optical Fiber to timing clients. Uses commercial hardware (MicroResearch Finland) ►So far for the electron side, there are >80 EVRs (mostly PMC) and >10 fanout modules.

7. DEVDEV LCLS Timing/Event System Architecture ~ Linac main drive line Sync/Div SLC MPG PNETPNET 119 MHz 360 Hz SLC events LCLS events PNETPNET PP PDUPDU EVREVR OCOC TTL-NIM convert. Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons TTL SLC Trigs FANFAN OCOC Low Level RF EPICS Network Precision<10 ps fiber distribution LCLS Timing System components are in RED *MicroResearch * * EVGEVG LCLS Master Oscillator 476 MHz Linac Master Osc System is based around the EVent Generator and EVent Receiver FIDOPDU Raw 360 Hz LCLS Timeslot Trigger

8. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 8 LCLS Systems – Master Timing Rack 119MHz Synchronizer Chassis Contains: VME CPU VME PNET Rx EVG Master Fanouts Master Timing Crate Master FODU Connects fibers to Long-Haul Trunks for entire machine

9. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 9 LCLS Timing System – BPM Client Rx FODU & Fanout Crate BPM Crate w/VME-EVR Rear of BPM Crate / Showing Trigger Rear Transition Module

10. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 10 LCLS Timing System – Other Clients Toroid Crate w/PMC-EVR Rear of Toroid Crate / Showing Trigger Rear Transition Module Profile Monitor Crate w/ (4) CPUs & PMC-EVRs MCOR Magnet Crate

11. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 11 Event System Requirements Event Generator IOC : Send out proper event codes at 360Hz based on: PNET pattern input (beam code and bits that define beam path and other conditions) Add LCLS conditions such as BPM calibration on off-beam pulses, diagnostic pulse etc. Future – event codes also based on new MPS and user input Send out timing pattern, including EPICS timestamp with encoded pulse in nsec. part on timing fiber Manage user-defined beam-synchronous acquisition measurement definitions

12. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 12 Event System Requirements, cont Event Receiver IOC: Set trigger delays, pulse widths, and enable/disable via user requests (not yet done on a pulse-by-pulse basis) Set event code per trigger (triggering done in HW when event code received) Receive timing pattern 8.3 msec before corresponding pulse. Provide EPICS timestamp to record processing. Perform beam-synchronous acquisition based on tags set by EVG in the timing pattern. Process pre-defined records when specific event codes are received – not used much yet.

13. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 13 EVR IOC Time Line – 1 Beam Pulse (B0) F0 0 Fiducial Time (usec) B0 Acq Trigger 1023 Beam Kly Standby Record processing (event, interrupt) Fiducial Event Received Event Timestamp, pattern records, and BSA ready Receive pattern for 3 pulses ahead Hardware Triggers ~500 0.3 ~40 100 Triggering Event Codes Kly Accel F1 Fiducial … 2778 110 StartEnd

14. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 14 Issues and Tasks Modifications to EVG HW and firmware for 119MHz clock input and AC line input. Had to power cycle a fanout module after an EVG power cycle. Changing an event code for a specific trigger requires a change in the delay to trigger at the same time – need database to automate the change. “Trigger Storms”: Due to LCLS Master Osc unlocking / Fix: New MO / De- Couple LCLS Timing Sys from it (connect direct to MDL). Need interface to MPS over private UDP at 360hz. Need global kicker control (single-shot, burst) done by EVG instead of locally. Record processing at beam rate (up to 120hz) – some processing delays seen: Too many records in one lockset. Some records pick up wrong timestamp when delayed too long and data cannot be correlated with other data on other IOCs. Some records need to have TSE field properly set. Too many CA clients monitoring PVs at beam rate instead of snapshot PVs provided at a slower rate. Not an issue but interesting - some beam diagnostic (ie, BPM) IOC engineers choosing to trigger at max possible rate and then use the timing data to decide if record processing required or to set record severity.

15. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 15 Linac Upgrade List When 2 event codes trigger a device on the same pulse, the second event restarts the delay. The second event must be ignored instead. Interrupt from the EVG on fiducial trigger (AC line trigger). Diagnostics from the fanout modules. Need status of the RF clock into the control system. Upgrade front end timing hardware. Move functions from the old timing system master pattern generator to the EVG IOC.

16. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 16 End of Talk – Thank you!

17. Stephanie Allison/John Dusatko EPICS Collaboration Meeting saa@slac.stanford.edu May 1, 2009 17 Timing Requirements Maximum trigger rate 360 Hz Clock frequency 119 MHz Clock precision 20 ps Coarse step size 8.4 ns ± 20 ps Delay range >1 sec Fine step size 20 ps Max timing jitter w.r.t. clock 2 ps rms Differential error, location to location 8 ns Long term stability 20 ps