1. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 1 Today: Verilog and Sequential Logic zFlip-flops yrepresentation of clocks - timing of state changes yasynchronous vs. synchronous zFSMs ystructural view (FFs separate from combinational logic) ybehavioral view (synthesis of sequencers) zSequential don't cares

2. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 2 module dff (CLK, d, q); input CLK, d; output q; reg q; always @(CLK) q = d; endmodule Incorrect Flip-flop in Verilog zUse always block's sensitivity list to wait for clock to change Not correct! Q will change whenever the clock changes, not just on the edge.

3. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 3 module dff (CLK, d, q); input CLK, d; output q; reg q; always @(posedge CLK) q = d; endmodule Correct Flip-flop in Verilog zUse always block's sensitivity list to wait for clock edge

4. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 4 module dff (CLK, s, r, d, q); input CLK, s, r, d; output q; reg q; always @(posedge CLK) if (r) q = 1'b0; else if (s) q = 1'b1; else q = d; endmodule module dff (CLK, s, r, d, q); input CLK, s, r, d; output q; reg q; always @(posedge r) q = 1'b0; always @(posedge s) q = 1'b1; always @(posedge CLK) q = d; endmodule More Flip-flops zSynchronous/asynchronous reset/set ysingle thread that waits for the clock ythree parallel threads – only one of which waits for the clock SynchronousAsynchronous

5. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 5 Example: A parity checker zSerial input string yOUT=1 if odd # of 1s in input yOUT=0 if even # of 1s in input Present Input Next Present State State Output Even 0 Even0 Even 1 Odd0 Odd 0 Odd1 Odd 1 Even1 1. State diagram and state-transition table

6. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 6 Example: A parity checker (continued) 2. State minimization: Already minimized yNeed both states (even and odd) yUse one flip-flop 3. State assignment (or state encoding) Present Input Next Present State State Output 0 0 0 0 0 1 10 1 0 11 1 1 0 1

7. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 7 Example: A parity checker (continued) 4. Next-state logic minimization yAssume D flip-flops yNext state = (present state) XOR (present input) yPresent output = present state 5. Implement the design

8. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 8 module FSM (CLK, in, out); inputCLK; inputin; outputout; regout; // state variable reg [1:0]state; // local variable reg [1:0]next_state; always @(posedge CLK) // registers state = next_state; always @(state or in) // Compute next-state and output logic whenever state or inputs change. // (i.e. put equations here for next_state[1:0]) // Make sure every local variable has an assignment in this block! endmodule Verilog Structural View of a FSM zGeneral view of a finite state machine in verilog

9. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 9 `define zero 0 `define one1 1 `define two1s 2 module reduce (CLK, reset, in, out); input CLK, reset, in; output out; reg out; reg [1:0] state;// state variables reg [1:0] next_state; always @(posedge CLK) if (reset) state = `zero; else state = next_state; state assignment Moore Verilog FSM zReduce 1’s example 1 0 0 0 1 1 zero [0] one1 [0] two1s [1]

10. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 10 always @(in or state) case (state) `zero: // last input was a zero begin if (in) next_state = `one1; else next_state = `zero; end `one1: // we've seen one 1 begin if (in) next_state = `two1s; else next_state = `zero; end `two1s: // we've seen at least 2 ones begin if (in) next_state = `two1s; else next_state = `zero; end endcase crucial to include all signals that are input to state and output equations Moore Verilog FSM (continued) note that output only depends on state always @(state) case (state) `zero: out = 0; `one1: out = 0; `two1s: out = 1; endcase endmodule

11. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 11 module reduce (CLK, reset, in, out); input CLK, reset, in; output out; reg out; reg state;// state variables reg next_state; always @(posedge CLK) if (reset) state = `zero; else state = next_state; always @(in or state) case (state) `zero: // last input was a zero begin out = 0; if (in) next_state = `one; else next_state = `zero; end `one: // we've seen one 1 if (in) begin next_state = `one; out = 1; end else begin next_state = `zero; out = 0; end endcase endmodule Mealy Verilog FSM 1/0 0/0 1/1 zero one1 Input Remember the Highlight- The-Arrows Method Output

12. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 12 always @(posedge CLK) begin temp = B; B = A; A = temp; end always @(posedge CLK) begin A <= B; B <= A; end Blocking and Non-Blocking Assignments zBlocking assignments (X=A) ycompletes the assignment before continuing on to next statement zNon-blocking assignments (X<=A) ycompletes in zero time and doesn’t change the value of the target until a blocking point (delay/wait) is encountered zExample: swap

13. CSE 370 - Spring 1998 - Verilog for Sequential Systems - 13 RTL Assignment zNon-blocking assignment is also known as an RTL assignment yif used in an always block triggered by a clock edge ymimic register-transfer-level semantics – all flip-flops change together // B,C,D all get the value of A always @(posedge clk) begin B = A; C = B; D = C; end // implements a shift register too always @(posedge clk) begin B <= A; C <= B; D <= C; end // this implements a shift register always @(posedge clk) begin {D, C, B} = {C, B, A}; end