1. 1/28 ECE 753 8 th May 2014 H ardware Implementation of Self-checking circuits on FPGA Project Team #1 Chandru Loganathan Sakshi Gupta Vignesh Chandrasekaran Spring 2014

2. 2/28 Structure of the Talk 1.Motivation and Introduction 2.Totally self-checking circuits and Reconfiguration logic 3.Less than or equal to checker 4.Non increasing sorting checker 5.Range checker 6.Residue checker 7.Future scope

3. 3/28 Introduction In a Totally Self-checking Circuit (TSC), if there is a fault in the inputs and/or within the TSC itself, the system no longer functions as desired. If any of the input is faulty, then the TSC brings the complete system to halt. Having a reconfiguration logic can leverage that. Reconfiguration logic allows the system to function properly in presence of at most two faults. Motivation of this project is to make the most of the available hardware without having to compromise on the fault tolerance of the output.

4. 4/28 Basic Definitions A circuit is said to be fault secure if in the presence of a fault, the output is either always correct, or not a code word for valid input code words. A circuit is said to be self-testing if only valid inputs can be used to test it for faults. A circuit is said to be totally self-checking if it is both fault secure and self-testing.

5. 5/28 Totally Self-checking Checker (TSC) A TSC has 4 inputs and 2 outputs Hence, 4 possible output combinations are possible (00, 11, 01, 10)

6. 6/28 Totally Self-checking Checker (TSC) Two-rail checker

7. 7/28 * denotes a two-rail self-checker circuit Totally Self-checking Checker (TSC) Multi-bit TSC

8. 8/28 Reconfiguration Logic When there is a fault in any one of the inputs or in the TSC itself, then the system halts. In order, to prolong system halt we introduce Reconfiguration Logic. If a non-code word (00 or 11) output is detected from the TSC, then the Reconfiguration Logic Enable (logic high) signal is triggered. Now, the reconfiguration logic identifies the faulty line and masks it. New x 0, y 0, x 1, y 1 values are computed and fed into a multiplexer. The multiplexer selects between the new values and old values of x 0, y 0, x 1, y 1 and outputs the final values of x 0, y 0, x 1, y 1.

9. 9/28 Reconfiguration Logic Algorithm for Reconfiguration logic

10. 10/28 TSC with Reconfiguration Logic Block Diagram

11. 11/28 TSC with Reconfiguration Logic Analytical comparison Without reconfiguration logic With reconfiguration logic

12. 12/28 Implementation Analysis Checker CircuitNumber of Sliced LUTs Number of LUT flip flop pairs used Worst case combinational delay (ns) TSC (1 bit)224.494 TSC (16 bit)49 12.555 Reconfiguration logic (16 bit) 32 4.678 TSC with reconfiguration logic (16 bit) 64 18.713

13. 13/28 There are three types of errors encountered in sorting algorithm: – Functional error: Operands are incorrectly ordered – Data error: One or more bits of the operands are changed – Hybrid error: Where both functional and data errors occur simultaneously LTOETC compares two consecutive non-negative numbers and checks if they are in correct order. Non-increasing sorting checker

14. 14/28 Suppose two non-negative numbers N 1 and N 2 are represented as x 1,x 2,…,x k and y 1,y 2,…,y k. X 1 = x 2,…,x k and Y 1 = y 2,…,y k Valid input code space: – x 1 y 1 = 00 and X 1 ≥ Y 1 – x 1 y 1 = 11 and X 1 ≥ Y 1 – x 1 y 1 = 10 and X 1 ≥ Y 1 – x 1 y 1 = 10 and X 1 < Y 1 Above code space denotes that N 1 ≥ N 2 and the output of LTOETC block must be a valid codeword. LTOETC

15. 15/28 LTOETC Block Diagram Reference: D.L. Tao, “A Self-Testing Non-increasing Order Checker”, IEEE Transactions on Computers, Vol. 46, No. 7, pp. 817-820, July 1997.

16. 16/28 x 1 y 1` (X 1, Y 1 )co 1 co 2 a 11 a 12 b 11 b 12 c1c2c3c4c1c2c3c4 a 21 a 22 b 21 b 22 a 31 a 32 b 31 b 32 o 1 o 2 00X 1 ≥ Y 1 11011010001100011001 11X 1 ≥ Y 1 11001101001001 01 10X 1 ≥ Y 1 11110000010011110010 X 1 < Y 1 00100100100110001110 00X 1 < Y 1 00001110101110110111 X 1 < Y 1 000110 1111011111 01X 1 ≥ Y 1 00100111001101011111 01X 1 < Y 1 00110011101111110111 LTOETC Input code space

17. 17/28 LTOETC is code disjoint: – Different inputs follow different output routes. LTOETC is self-testing: – Each functional block receives all necessary test vectors. Hence, it is fully tested during normal operation. – Fault in each functional block will be excited which therefore generates a non- code-word at o 1 o 2 of LTOETC LTOETC Properties

18. 18/28 Implemented a design which detects only functional errors in ordered set of inputs. Considered 5 input numbers in order Non-increasing sorting checker Block Diagram Reference: D.L. Tao, “A Self-Testing Non-increasing Order Checker”, IEEE Transactions on Computers, Vol. 46, No. 7, pp. 817-820, July 1997.

19. 19/28 Non-increasing sorting checker Simulation Inputs when in non-increasing order generate a valid code word Functional error in sorting order generates non-code word, i.e., o 1 o 2 = 11

20. 20/28 The checker circuit detects whether the input lies within a specified range. Input out of bound generates a non-code word, i.e., o 1 o 2 = 11 Input within the range generates a valid code word Range Checker Block Diagram

21. 21/28 Simulation Range Checker Input value for the first set of upper and lower range generates valid code word. Input value when out of range for the second case generates non-code word.

22. 22/28 Implementation Analysis Checker CircuitNumber of Sliced LUTs Number of LUT flip flop pairs used Worst case combinational delay (ns) Non-increasing sorting checker 70 8.636 Range checker34 6.958

23. 23/28 Residue Checker Based on the idea of computing the residue of a given function for a given modulo and comparing it against the residue obtained by computing the same function broken down by modulo arithmetic. Property 1: m = m + m > m Property 2: m = m * m > m Consider a multiple-accumulate (MAC) unit of a processor which computes the following function: Z = A*B+C

24. 24/28 Residue Checker m = m m = m * m > m + m > m Block Diagram Reference: S.Wei and K.Shimizu, “Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 72-77, Oct. 2001

25. 25/28 Residue Checker Modulo checkers can be implemented in several ways in hardware. 2 n Modulo checker Bit select the lower n bits of the applied input. Hardware conservative. Lesser combinational delay. General modulo checker Residue for any value of modulo. Demands more hardware compared to the earlier method. Relatively slower clock rate. Modulo Checker

26. 26/28 Residue Checker Hardware utilization for each of the implementation is different. As the value of modulo increases, the hardware utilization increases. Hardware utilization is the measure of the number of LUTs utilized on the FPGA. Hardware complexity can be expressed as function of modulo. Timing. Performance matrix

27. 27/28 Residue Checker HC(m) = 4.2814ln(m) + 5.275 Hardware Complexity: 2 n Modulo checker

28. 28/28 Residue Checker HC(m) = 27.319ln(m) + 186.95 Hardware Complexity: General modulo checker

29. 29/28 Residue Checker Mix of both designs Multiplex both and choose according to Modulo. This hybrid is ideally suited for various application.

30. 30/28 Implementation details Design was implemented on Xilinx Spartan 6 XUPV5LX110T FPGA Synthesis was done with Xilinx ISE 14.7 Simulation was done using ModelSim Debugging was done using ChipScope Pro.

31. 31/28 Future Scope Reconfiguration logic Can be introduced in all hardware redundant circuits. Can be scaled to every design. Must be made fault secure

32. 32/28 Questions?

33. 33/28 Thank you