1. On the Selection of Efficient Arithmetic Additive Test Pattern Generators S. Manich, L. García, L. Balado, E. Lupon, J. Rius, R. Rodriguez, J. Figueras Universitat Politècnica de Catalunya, UPC

2. Outline Introduction Motivation State of the art Objective Proposed technique Experimental results Conclusions

3. System on Chip (external test access is difficult)

4. Moore’s Law for Test: Fab vs. Test Capital SIA Roadmap Data 2001

5. Using BIST for DFT BIST e.g. LFSR’s

6. Reusing internal datapaths Increment Adder Accumulator Test Vectors DATAPATH First proposed by Rajski and Tyszer. Similar LFSR behavior. Proved by Chiusano, Prinetto and Wunderlich Test Pattern Generator Signature Analyzer

7. Comparison of test sequences LFSR AdTPG 119 test vectors

8. Comparison between LFSR and AdTPG c3540, fault coverage of stuck-at. No reseeding Test vector Fault coverage AdTPG LFSR

9. Drawbacks of the AdTPG

10. Memory size doubles Seed 1 MEMORY Seed 1 Increment 1 MEMORY LFSR AdTPG l1

11. Memory size doubles Seed 1 Seed 2 MEMORY Seed 1 Increment 1 Seed 2 Increment 2 MEMORY LFSR AdTPG l1 l2

12. Memory size doubles Seed 1 Seed 2 Seed 3 MEMORY Seed 1 Increment 1 Seed 2 Increment 2 MEMORY Seed 3 Increment 3 LFSR AdTPG l1 l2 l3l2 l3

13. Memory size doubles Seed 1 Seed 2 Seed 3 Seed 4 MEMORY Seed 1 Increment 1 Seed 2 Increment 2 MEMORY Seed 3 Increment 3 Seed 4 Increment 4 LFSR AdTPG l1 l2 l3 l4 l2 l3 l4 SI triplet

14. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1 Seed

15. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1 Increment

16. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

17. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

18. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

19. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

20. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

21. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

22. Generation period less than 2 n 000...0 001...1 011...1 101...1 111...1

23. Unswitched input signals during test LFSR AdTPG 119 test vectors

24. Unswitched input signals during test LFSR AdTPG 119 test vectors Shadow from 11...11 substring Shadow from 00...01 substring

25. Proposed methodology LUCSAM

26. Using same value for seed and increment Increment Adder Accumulator Test Vectors DATAPATH Seed 1 Seed 2 Seed 3 Seed 4 MEMORY l1 l2 l3 l4 SS triplet k-triplet set

27. Always generate odd increments Seed Increment LSB 1 1

28. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

29. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

30. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

31. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

32. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

33. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

34. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

35. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

36. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

37. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

38. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

39. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

40. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

41. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

42. Period of the test sequence is 2 n 000...0 001...1 011...1 101...1 111...1

43. Avoid shadow zones in test sequence Limit the size of substrings 11...11 or 00...01 Rule of thumb: “Any input switchs at least one time” Increment 00.......0111.......1100.......0111.......11 T (test length) A (maximum subgroup size)

44. Proposed methodology Procedure preparation of k-triplet set for circuit C and a fault set  Define target FC * and initial lenght L Run ATPG(C,  ) to generate initial test set S (initial set of seeds) for target FC * While FC < FC * do For all seeds in S do Run HiFault(AdTPG(seed,seed’,L),C,  ) and calculate FC end do Select seed giving maximum FC increase Reduce set , set S and calculate length l Append in k-triplet set the SS triplet (seed,l) end do end procedure

45. Proposed methodology Fault Set Circuit ATPG Test Set

46. Proposed methodology Fault Set Test Set AdTPG Test sequence Fault simulator Seed1(l1)

47. Proposed methodology Fault Set Test Set AdTPG Test sequence Fault simulator Seed1(l1)Seed2(l2) Seed1

48. Proposed methodology Fault Set Test Set AdTPG Test sequence Fault simulator Seed1(l1)Seed2(l2)Seed3(l3) Seed1 Seed2

49. Proposed methodology Fault Set Test Set AdTPG Test sequence Fault simulator Seed1(l1)Seed2(l2)Seed3(l3)Seed4(l4) Seed1 Seed2 Seed3

50. Proposed methodology Fault Set Test Set AdTPG Fault simulator k-triplet set Seed1(l1)Seed2(l2)Seed3(l3)Seed4(l4) Seed1 Seed2 Seed3 Seed4

51. Experimental results. Fault coverage LUCSAM Previous published data 15 circuits 5 circuits s953 s838 s5348 s420 s1196

52. Experimental results. Bits stored in memory LUCSAM Previous published data 20 circuits 0 circuits

53. Experimental results. Total test length LUCSAM Previous published data 17 circuits 3 circuits c5315 s820 c2670

54. Fault coverage evolution of c2670 Test vector Fault Coverage 95.31% Seed1Seed2Seed3Seed4

55. Checking size of 11...1 or 00...0 subgroups Size of subgrup # substrings Less than 1.31% Random vectors ATPG vectors No risk of shadows using ATPG

56. Conclusions Verified that AdTPGs is a valid TPG. Memory size is reduced if Seed and Increment use same value. No lose of performances. LSB of increment masked to 1 to allow generation of all 2 n values. Unswitching of input signals may be prevented by cautious detection of large 11...11 and 00...01 subgrups. LUCSAM: proposed algorithm selecting the best seeds from initial ATPG test vectors. Results show good behavior of the methodology. Average values are FC = 98.77 %, Memory = 783 bits and test length = 2398 vectors.

57. Future work Some capabilities are observed from the AdTPG. Test session preparation from RTL analysis. Better suited for input activity (power) reduction. Limitations are also observed. More difficult generation of test vectors for scan-path. Datapath register smaller than some circuit inputs.

58. Results for ISCAS’85

59. Results for ISCAS’89