1. April 30, 2014 1 Latest Developments in MIPI Specifications April 30, 2014 Yoav Lavi VLSI Plus Ltd

2. April 30, 2014 2 2 AGENDA Introduction to MIPI® MIPI® standards - scope How MIPI® standards are created MIPI® CSI2 standard for camera to processor interface VLSI Plus’ CSI2 compliant IP cores Selected MIPI® third generation standards: MPHY UNIPRO CSI3 VLSI Plus’ Roadmap

3. April 30, 2014 3 Who Are We? Experts in VLSI Design and Architectures Providing Engineering Services to the VLSI community Providing specialized IP cores Per customer tailoring Located in Israel Contributor – level MIPI member since 2005

4. April 30, 2014 4 4 MIPI ® (Mobile Industry Processor Interface) Industry consortium Creates standards for interface between components of mobile devices Started by Nokia and ST 252 Members (as of April 2014): 5 Founder Members (Nokia, ST, Intel, TI, Samsung) 81 Contributor Members 165 Adopter Members 1 Promoter Member

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6. 6 6 MIPI ® - the Creation of Standards MIPI ® - the Creation of Standards MIPI® has a technical steering committee, which guides a multitude of Working Groups Typical Working Group has 40 members; some 15 are active When a Working Group works on a standard, weekly phone conferences are held (typically 3 hours each), in addition to many emails and documents In addition, every three months there is a F2F meeting Each WG had a Chairman who makes sure that the group is on schedule, and that due technical diligence is done to all parts of the spec. Participants present technical arguments, according to the viewpoint of their companies; e.g. some participants look at easy SW implementation, while others are concerned mainly with low power consumption Each standard has several Draft stages Major Draft stages as well as final versions undergo a period of all members review and subsequent vote Final draft is approved / disproved by MIPI BOD

7. April 30, 2014 7 7 Camera Serial Interface 2 (CSI-2) Introduction Working Group (CWG) started by MIPI® in March 2004 In June 2004 MIPI® Technical Steering Group recommended that Display and Camera Interfaces should use the same Physical layer – the D-PHY, which was being developed by the PHY Working Group At some point It was suggested that the CWG will adopt SMIA CCP2. This proposal was rejected CSI2 over D-PHY is superior to CCP2 - it allows faster rate at lower power consumption, adds LP signaling, and more

8. April 30, 2014 8 CSI2 camera-processor link

9. April 30, 2014 9 9 Camera Serial Interface 2 (CSI-2) D-PHY Highlights 1 DDR Clock Lane 1 to 4 Data Lanes High Speed Differential Mode for data transfer Low Power Mode, using CMOS levels on the two conductors of each pair, for low speed signaling Low Power Mode is entered between packets  reduced overall power consumption Original speed target – 500M bps per lane (“D”) First implementations stopped at 1Gbps Current version limit - 1.5Gbps. 8 lanes extended-DPHY (non-DPHY) are in the market

10. April 30, 2014 10 Camera Serial Interface 2 (CSI-2) DPHY Universal Lane Module Functions

11. April 30, 2014 11 The processor controls the camera via two CCI lines (not part of DPHY) Camera sends packets of data to the processor via DPHY lanes Packets can be Short (32 bit) or Long All packets have an 8 bit ECC filed in the Header, allowing correction of any single-bit error and detection of all two-bit errors Short packets are sent to indicate events and to time synchronization (e.g. FS, FE, LS, LE) Long packets are used to send video lines and user defined data Camera Serial Interface 2 (CSI-2) Highlights (A)

12. April 30, 2014 12 Long packet header comprises the following fields: Data-Type, defining one of 19 video formats Virtual channel selection Length of the packet, in bytes 8-bit ECC Long packets end with a 16 bit CRC For each of the 19 video formats, bit ordering is defined Optional DPCM data compression – 10 or 12 bit pixels can be compressed to 8, 7 or 6 bits per pixel Camera Serial Interface 2 (CSI-2) Highlights (B)

13. April 30, 2014 13 VLSI Plus IP Product Portfolio ProductDescriptionStandardsRatingMaturity SVR-CS4 Serial Video Receiver, 1-4 data lanes CSI2, DPHY 4x1.5Gbps Mature product SVR-CS4-F FPGA version of SVR-CS4 CSI2, DPHY Typically 4x850mbps Mature product SVT-CS4-AP1 Serial Video Transmitter, 1-4 data lanes CSI2, DPHY 4x1.5Gbps Silicon ramp-up SVT-CS4-AP1-F Serial Video Transmitter, 1-4 data lanes CSI2, DPHY Typically 4x850mbps Mature Product A: First Generation CSI2 Rx/Tx Cores

14. April 30, 2014 14 SVTCS4-AP1 – Serial Video Transmitter for CSI2; 1-4 data lanes ASIC and FPGA Versions 1-4 lanes, Low gate count Modular – generic core and customized application package Optional hardware for CSI2/DPHY link test Optional DPCM compression

15. April 30, 2014 15 SVR-CS4 Block Diagram

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17. April 30, 2014 17 VLSI Plus IP Product Portfolio B: Second Generation CSI2 Rx/Tx Cores ProductDescriptionStandardsRatingMaturity SVRPlus-CSI2-I Serial Video Receiver, 1-8 data lanes, 1-4 pixel output per clock,64 bit internal data path Extended CSI2, DPHY 8x1.5Gbps new product SVRPlus-CSI2-F FPGA version of SVRPlus-CSI2-I Extended CSI2, DPHY 8x1.5Gbps Mature product SVTPlus-CSI2-AP1 Serial Video Transmitter, 1-8 data lanes, 1-4 pixel input per clock,64 bit internal data path Extended CSI2, DPHY 8x1.5Gbps New product SVT-CS4-AP2 Multiplexing Serial Video Transmitter, 12 video sources, 1-4 data lanes CSI2, DPHY 4x1.5Mpbs New product

18. April 30, 2014 18 Second Generation CSI2 Receiver – the SVRPlus-CSI2-I Configurable 1 or 2 clock lanes; 1,2,3,4 or 8 data lanes 64 bit internal data bus Configurable 1, 2 or 4 pixels output per clock Up to 1.5Gbps per lane; Extensive set of registers, accessible by AMBA APB bus Support of all video formats Programmable timing parameters Support of CSI2 DPCM decompression Optional output FIFO for continuous output streams Error counting hardware, for on-line BER measurements For Recently Introduced of the line sensors.

19. April 30, 2014 19 Second Generation CSI2 Receiver – the SVRPlus-CSI2-I Simplified Block Diagram:

20. April 30, 2014 20 Simplified Block Diagram: SVT-CS4-AP2 – Multiplexing CSI2 Serial Video Transmitter Multiplex up to 12 independent video sources Multiplex base is virtual-channel/data type combination Supports DPCM compression

21. April 30, 2014 21 MIPI Camera Interface - Next Generation

22. April 30, 2014 22  BURST mode operation for improved power efficiency  Multiple transmission modes with different bit-signaling and clocking schemes  Multiple transmission speed rates per BURST mode for better bandwidth utilization and for mitigation of interference problems.  Fixed rates for high-speed mode, flexible (within ranges) for low-speed mode.  Multiple power saving modes  Symbol coding (8b10b) for spectral conditioning, clock recovery, and in-band control options for both PHY and Protocol level  Clocking flexibility: independent local reference clock or shared clocks MPHY Benefits (A)

23. April 30, 2014 23  Optical friendly: enables low-complexity electro-optical signal conversion and optical data transport inside the interconnect between MODULEs  Optimized for short interconnect (<10 cm); extendable to a meter with optical converters and optical waveguides.  Configurability: differences in supported functionality (to reduce cost) enables tuning and implementation for best performance MPHY Benefits (B)

24. April 30, 2014 24 UNIPRO and CSI3

25. April 30, 2014 25 VLSI Plus Next Generation IP products ProductDescriptionStandardsIntroduction SVTPlus-CSI2-AP2 Multiplexing Serial Video Transmitter, 12 video sources,, 1-8 data lanes, 1-4 pixel input per clock,64 bit internal data path CSI2 1.4 DPHY 2.0 CPHY 1.0 Q4 SVR_CS2_3G Third generation CSI2 SVR CSI2 1.4 DPHY 2.0 CPHY 1.0 Q4 V_PRO14 MIPI UNIPRO1.4 compliant IP core UNIPRO 1.4 MPHYTBD SVR-CS3 MIPI CSI3 compliant serial video receiver CSI3 1.1 or 1.2 UNIPROMPHYTBD SVT-CS3 MIPI CSI3 compliant serial video transmitter CSI3 1.1 or 1.2 UNIPROMPHYTBD