1. 1/38 Alternative Substrates Y-C Jung,S-H Won, D.G. Ast

2. 2/38 The biggest strength of OLEDs is that they do not require a backlight and can be made thinner than any other technology used today. A 2 mm thick OLED is a reality today where the thinnest LCD is 3 mm” Sharp http://www.sharpsma.com/lcd/lcdguide/Technologies/Tech_index.php

3. 3/38 The US Army provided the core funding of $43.7 M to establish the Flexible Display Center at ASU. www.asu.edu/ia/photogallery/fdc/1.htm

4. 4/38 Outline 1 Overview 2 Polymer Substrates 3. Flexible Glass Substrates 4. Processing Corning Microsheet 5. Results 6. Summary

5. 5/38 CTE PET 65 10 -6 / o C)CTE 00 MS 7.4 10 -6 / o C)  -Si:H LTO α-Si:H T < 300 °C T< 600 °C Polymers Borosilicate Glass ELA poly-Si + 1  m SiO 2 LPCVD poly-Si MILC silicon ELA poly-Si CTE Si 2.6 10 -6 / o C) LTO, Annealed LTO CTE Si 2.6 10 -6 / o C) 1. Overview Better match: Glass !

6. 6/38 2. Polymer Substrates Uncoated : Oxygen, Water Transmission: 1 … 100 g/m 2 / da y Coated with 4 inorganic layer (Vitex)

7. 7/38 “Due to accumulated internal stresses, optimisation of composition, stress and adhesion for each layer is needed in order to avoid warping of the substrate and cracking of the layers during deposition and/or laser annealing. Such stresses arise, for the most part, from difference in CTE of the plastic substrate and inorganic layers”. SID 03 Digest. Paper 47.1 High Performance Plastic Substrates for Active Matrix Flexible FPD. Simone Angiolini, Mauro Avidano, Roberto Bracco, Carlo Barlocco Specialty Mat erials, Ferrania Imaging Technologies, Italy ; Nigel D. Young, Michael Trainor Philips Research Laboratories, UK; Xiao-Mei Zhao Electronic Materials, Promerus LLC, USA] Elaborate Adhesion and Stress Management required Up to 13 inorganic layers with CTE 1/30’th of polymer may have to be deposited on polymer!

8. 8/38 The most difficult step of poly-Si on plastics Electronics PECVD SiO 2 must be 5 to 10 times thicker than channel www.FlexIcs.com

9. 9/38 Intel-funded plastic IC firm folds, assets up for sale Plastics on semiconductor technology is not new..but difficult to manufacture and commercialize

10. 10/38 3. Flexible Glass Substrates Solve most of CTE induced stress problems Permit process temperatures in excess of 600 o C Can use sintered semiconductors (e.g. inkjet printed nano-slurries) Are available from two rivaling glass companies

11. 11/38 Corning 0211 Microsheet Borosilicate Glass ~50…~100  m (00,0) CTE : 7.4….8.4 x 10 -7 / o C

12. 12/38 Corning Microsheet Schott D263 SiO 2 (65wt%) SiO 2 (64%), Al 2 O 3 (2wt%)…… dopant Al 2 O 3( 4%), B 2 O 3 (9wt%)…….. Dopant B 2 O 3 (8%), Na 2 O (7wt%)……. GB  collapse Na 2 O 6%, K 2 O (7wt%) …….. GB  collapse ZnO (7wt%) ……. Deep state: 0.3,0.6eV 3% not listed 18% not listed Commercial Products

13. 13/38 Mechanical Properties (Schott D 263) Influence of edge and surface coating on strength. R=30mm; p fail <1% Fracture strength of glass A upp er edge (initial scribing) and B l ower edge. Radii of 30 mm; failure < 1% Armin Plichta, Andreas Habeck, Silke Knoche, Anke Kruse, Andreas Weber, Norbert Hildebrand in Ch. 3 “Flexible Glass Substrates” in “Flexible Flat Panel Displays”, Wiley-SID Seri es in DisplayTechnology, Ed.: Gregory P. Crawford, ISBN: 9780470870488 Online ISBN: 9780470870501;

14. 14/38 4 Processing Microsheet 1. Anodic Bonding to a Si wafer, release via release a la surface MEMS 2. Peripheral Anodic Bonding to Si wafer, release by cutting, sacrificing edge 3. Anodic bonding to flexible Si structures, e.g. pillars, springs 4. Floating on liquid metal    5. Minature version of susceptor slot, created on carrier wafer    4.1 Options to process flexible, ultra-thin glass in a conventional line

15. 15/38 Anodic Bonding, 350 o C, 10N, 1000V Failure mode: Delayed fracture, driven by 0.2% residual tensile strain

16. 16/38 Ga x In 1-x bonding Failure mode: Microsheet edge lift of during CNF required RCA clean

17. 17/38 Rectangular substrate, diamond cut, good edge finish “Pocket” carrier system, fabricated on 4” Si wafer:

18. 18/38 4.2.1 Furnace Mixed (580 o C) precursor + 600…620 o C Furnace Anneal (Oxidized 4” Si) 4.2.2 RTA Mixed (580 o C) precursor + 650 o C Rapid Thermal Annealin 4.2.3 ELA Amorphous (500 o C) precursor + Excimer Laser Annealing 4 Processing Microsheet 4.2 Processes Used to fabricate TFTs on oxidized Si and Microsheet

19. 19/38 Poly-Si TFT Structure Baseline on oxidized Si wafer Barrier coated Microsheet

20. 20/38 4.1. Mixed amorphous/x-stalline 580 o C precursor 620 o C, 24 hr Anneal 4. Results

21. 21/38 Mixed Precursor/Furnace (or RTA)

22. 22/38 Mixed a/x-stalline Si Precursor: Structure peak of Poly Si Mixed Si 150 nm deposited at 580 o C LPCVD (silane) Temp : 580 o C Time : 30 min TEM XRD

23. 23/38 TEM of mixed amorphous, crystalline precursor, To be converted (620 o C furnace, 650 o C RTA) to fully poly-Si film.

24. 24/38 Vg(V) 40 30 20 10 Vd(V) 10 5 0.1 Transfer Characteristics * W/L = 55um/8um * Channel Mobility  7 cm 2 /Vs * a/x-stal mixture active layer: 580°C, 100nm * Gate oxide (LTO): 400°C, 100nm

25. 25/38 Hydrogenation - H 2 PECD System  300 o C, 80 sccm, 600 mTorr, 350W 580 o C precursor; 620 o C, 24 hrs, Reference wafer

26. 26/38 Failure Mode: Shorts CTE increases > 550 0 C Cool down - Cracks close - undetectable B.L. deposition BL at 620 o C Anneal Doremus: Glass Science. Jon Wiley and Sons

27. 27/38 Boron Profile after 24hr, 620 o C Anneal MicrosheetSiN x SiO 2 poly

28. 28/38 Failure Mode Summary Devices failed as shorts (100%) Traced to non-linear CTE of MS glass approaching T g Failure by CTE mismatch to barrier layer - not device silicon A more SiO 2 rich substrate (not commercially available) would. solve problem

29. 29/38 Mixed amorphous/x-stalline 580 o C precursor 650 o C, 100 Pulse RTA Anneal 4. Results (continued)

30. 30/38 TFT on Microsheet * a/x-stal precursor: 580°C, 100nm * Gate oxide (LTO): 400°C, 100nm - 650°C, 100 Pulse - Pulse time: 5 sec Low yield

31. 31/38 Excimer Laser Processing 4. Results (continued)

32. 32/38 ELA Process

33. 33/38 XRD of ELA annealed 500 o C a-Si) 124~361 mJ/cm 2, single pulse

34. 34/38 Vg(V) 40 30 20 10 Vd(V) 10 5 ELA; 500 o C a-Si ; 274 mJ/cm 2 ; Oxidized Si * a-Si active layer: 500 ° C, 100nm * Gate oxide (LTO): 400 ° C, 100nm * Annealing (500 °C, 4hrs.)

35. 35/38 Vd(V) 10 5 Vg(V) 45 35 25 * a-Si active layer: 500 ° C, 100nm * Gate oxide (LTO): 400 ° C, 100nm * Annealing (500 °C, 4hrs.) ELA ; 500 o C a-Si ; 274 mJ/cm 2 ELA; Microsheet

36. 36/38 Failure Mode Open - indicating insufficient doping activation Channel Resistivity ~ 10 6  cm indicative of undoped poly-Si

37. 37/38 Summary 1. Three methods to process Microsheet carry Microsheet in a line explored: a) Anodic bonding (full and partial) to 4” wafer b) InGa bonding to 4” wafer c) a MEMS fabricated carrier on 4” Si. 2. Three TFT processes investigated on two substrates (Microsheet, Si): - Amorphous Si with x-stal nuclei + 600 to 620 °C Furnace anneal - Amorphous Si with x-stal nuclei + 650 RTA anneal, Gla - Amorphous Si + Excimer Laser Annealing (ELA) 3. The upper temperature at which TFTs can be fabricated by cw (furnace) or (RTA) anneal limited by CTE difference between MS and the SiO 2 /SiN x barrier layer. Above about 550 °C, barrier layer fails in tension, permitting the out-diffusion of Boron which in turn shortens the TFT source to drain.

38. 38/38 Summary (continued) 4. Poly-Si TFTs can be fabricated on Microsheet with ELA (Excimer Laser Annealing using power densities of about 280 mJ/cm 2 ) 5. Future work ELA fabricated TFTs with hydrogen passivation from PECVD Nitride and simultaneous LTO densification using dummy absorber Acknowledgements This investigation was carried out with the financial support of Corning Inc. at the Cornell Nanofabrication Center, an NSF supported node in NSF NNUN network.

39. 39/38 BACK UP

40. 40/38 Finished 580 o C precursor; 620 o C Si TFT reference wafer