1. ECE 3450 M. A. Jupina, VU, 2014 Properties of Digital Circuits  Quantized States  Voltage Transfer Characteristic (VTC)  Voltage Levels  Noise Margins  Current Levels  Fan-In and Fan-out  Power Dissipation  Propagation Delay  Power-Delay Product  IC Packaging  Technology Trends of MOS Microprocessors and Memories

2. Some Key Lecture Objectives Before performing the Properties of Digital Circuits practicum, we need to look at the key properties of digital circuits used to compare one technology with another. How voltage levels of a technology not only define the logic states of a technology, but also lead to a definition of noise immunity for a technology. An understanding of how current levels, “loading,” power dissipation, and speed of operation are all inter-related. Reference: Fundamentals of Digital Logic, Chap 1, Sec 3.8, and App E.4. ECE 3450 M. A. Jupina, VU, 2014

3. Transistor-Transistor-Logic (TTL) TTL dominated the IC market from the 1960’s to early 1980’s. This picture changed in the 1980s due to two major factors: l Discrete logic gates in static CMOS became competitive in speed at a lower power cost. l The advent of programmable logic components such as PLDs and FPGAs made it possible to program complex random logic functions (equivalent to hundreds of TTL gates) on a single component. This results in a large reduction in board real-estate cost, while adding flexibility. ECE 3450 M. A. Jupina, VU, 2014

4. CMOS  CMOS stands for Complementary Metal-Oxide Semiconductor. MOS field-effect transistors (n- channel and p-channel) are used to construct logic gates.  FETs are voltage controlled and operate nearly as an ideal switch.  MOSFETs advantages: Lower power consumption than BJTs so billons of devices can be packed onto a single chip (MOSFETs or what are now known as FinFETs have dimensions in the deep sub-micron range). ECE 3450 M. A. Jupina, VU, 2014

5. CMOS ECE 3450 M. A. Jupina, VU, 2014 Currently, how small is the gate length of a FinFET? MOSFET FinFET Gate Length

6. Quantized States  Binary System possible states: 1 or 0, on or off positive logic: 1= high, 0 = low negative logic: 1= low, 0 = high  Future Systems – multilevel logic Ex:if three different on-off levels, then 2 3 = 8 logic states ECE 3450 M. A. Jupina, VU, 2014

7. VTC of a TTL Inverter Voltage Levels (V OH, V OL, V IL,V IH ) are defined at dV o /dV i = -1 VoVo ViVi ECE 3450 M. A. Jupina, VU, 2014

8. V out V in V OL 0V= V OH V DD = V T V IL V IH V DD V T –  V V Slope1–= VTC for a CMOS Inverter ECE 3450 M. A. Jupina, VU, 2014

9. Table of Voltage Levels for TTL Families ECE 3450 M. A. Jupina, VU, 2014

10. PSPICE Schematic of LS7404 TTL Inverter ECE 3450 M. A. Jupina, VU, 2014

11. PSPICE VTC Simulation of the LS7404 ECE 3450 M. A. Jupina, VU, 2014

12. PSPICE VTC Simulation of the LS7404 V IL = 0.7 V V IH = 1.18 V V OH = 4 V V OL = 0.15 V ECE 3450 M. A. Jupina, VU, 2014

13. Digital Properties Practicum Measured VTC of LS7404 ECE 3450 M. A. Jupina, VU, 2014

14. Voltage Level Definitions  V IH – High Level Input Voltage V input ≥ V IH to be recognized as a “1”  TTL Ex:V IH = 2V, thus at the input a “1” is between 2V and V CC ECE 3450 M. A. Jupina, VU, 2014

15. Voltage Level Definitions  V OH – High Level Output Voltage  TTL Ex:V OH = 2.4V, thus at the output a “1” is between 2.4V and V CC ECE 3450 M. A. Jupina, VU, 2014

16. Voltage Level Definitions  V IL – Low Level Input Voltage V input ≤ V IL to be recognized as a “0”  TTL Ex:V IL = 0.8V, thus at the input a “0” is between 0V and 0.8V ECE 3450 M. A. Jupina, VU, 2014

17. Voltage Level Definitions  V OL – Low Level Output Voltage  TTL Ex:V OL = 0.4V, thus at the output a “0” is between 0V and 0.4V ECE 3450 M. A. Jupina, VU, 2014

18. Logic Level Matching Levels at output of one gate must be sufficient to drive next gate. V OH > V IH V OL < V IL ECE 3450 M. A. Jupina, VU, 2014

19. Voltage Level Definitions  V LS – logic swing at the output V LS = V OH - V OL  Ideally, should be as large as possible. Higher V LS reduces ambiguity in the output logic state and increases noise immunity.  V LS defines the range of output voltages that define the unknown state, “X” state. ECE 3450 M. A. Jupina, VU, 2014

20. Voltage Level Definitions  V TW – transition width at the input V TW = V IH - V IL  Ideally, should be as small as possible. Lower V TW reduces ambiguity in the input logic state and increases noise immunity.  V TW defines the range of input voltages that define the unknown state, “X” state. ECE 3450 M. A. Jupina, VU, 2014

21. Voltage Levels Summary “1” “X” “0” “1” “X” “0” ECE 3450 M. A. Jupina, VU, 2014

22. Noise – unwanted variations of voltages and currents at the logic nodes V DD v(t) i(t) from two wires placed side by side –capacitive coupling voltage change on one wire can influence signal on the neighboring wire cross talk –inductive coupling current change on one wire can influence signal on the neighboring wire from noise on the power and ground supply rails –can influence signal levels in the gate Noise in Digital Circuits ECE 3450 M. A. Jupina, VU, 2014

23. Noise Margin Definitions  NM’s define the amount of noise immunity in the high or low level logic state.  NM H - High Level Noise Margin NM H = V OH - V IH  NM L - Low Level Noise Margin NM L = V IL - V OL  Ideally, the NM’s should be as large and as equal as possible.  NM of a technology = min{NM H, NM L }  TTL Ex:NM H = 2.4V - 2V = 0.4V NM L = 0.8V – 0.4V = 0.4V ECE 3450 M. A. Jupina, VU, 2014

24. Noise Superimposed on TTL Signals OR ECE 3450 M. A. Jupina, VU, 2014

25. Noise Margin Question A certain logic family has the following voltage parameters: V IH = 1.18 V, V OH = 4 V, V IL = 0.7 V, V OL = 0.15 V What is the largest positive-going noise spike that can be tolerated? What is the largest negative-going noise spike that can be tolerated? NM L = V IL – V OL = 0.55V NM H = V OH – V IH = 2.82V ECE 3450 M. A. Jupina, VU, 2014

26. PSPICE Noise Simulation Demonstrating the Concept of Noise Margin (LS7404) ECE 3450 M. A. Jupina, VU, 2014

27. PSPICE Noise Simulation V(IN) = Source + Noise V peak-to-peak V OH V OL ECE 3450 M. A. Jupina, VU, 2014

28. PSPICE Noise Simulation V(OUT) for Vpeak= 0, 0.5, 1, 3.1V V peak =0VV peak =0.5V V peak =1VV peak =3.1V ECE 3450 M. A. Jupina, VU, 2014

29. The Ideal Inverter The ideal gate should have –infinite slope (gain) in the transition region –high and low noise margins equal to half the logic swing –a gate threshold located in the middle of the logic swing –input and output impedances of infinity and zero, respectively –infinite output drive capability (infinite output current or fanout) V OUT V IN NM H = NM L = R i =  R o = 0 Fanout =  Ideal VTC V CC = V SUPPLY V OH = V CC V IL =V IH = V CC /2 V CC /2 V TW =0 (Impossible to be in X state) V OL = 0V V LS =V CC ECE 3450 M. A. Jupina, VU, 2014

30. Current Level Conventions Current out of a terminal is given as a negative value in Data Sheets. Current into a terminal is given as positive value in Data Sheets. ECE 3450 M. A. Jupina, VU, 2014

31. Table of Current Levels for TTL Families ECE 3450 M. A. Jupina, VU, 2014

32. Current Sourcing Versus Current Sinking ECE 3450 M. A. Jupina, VU, 2014

33. Current Level Definitions  I OL – Low Level Output Current Maximum current that an output terminal of a gate can sink when the output is “0”. If |I OUT | > |I OL |, then eventually V OUT > V OL  TTL Ex:I OL = +16mA, V OUT ≤ 0.4V I OUT “0” ECE 3450 M. A. Jupina, VU, 2014

34. Current Level Definitions  I IL – Low Level Input Current Maximum current that an input terminal of a gate can source when the input is “0”.  TTL Ex:I IL = -1.6mA, V IN ≤ 0.8V I IN “0” ECE 3450 M. A. Jupina, VU, 2014

35. Current Level Definitions  I OH – High Level Output Current Maximum current that an output terminal of a gate can source when the output is “1”. If |I OUT | > |I OH |, then eventually V OUT < V OH  TTL Ex:I OH = -400  A, V OUT ≥ 2.4V I OUT “1” ECE 3450 M. A. Jupina, VU, 2014

36. Current Level Definitions  I IH – High Level Input Current Maximum current that an input terminal of a gate can sink when the input is “1”.  TTL Ex:I IH = +40  A, V IN ≥ 2.0V I IN “1” ECE 3450 M. A. Jupina, VU, 2014

37. TTL Example – LED Load Which circuit would you use to drive an LED? (Assume that V LED = ~1.7 V.) + - 1.7 V I I - + 1.7 V ECE 3450 M. A. Jupina, VU, 2014

38. TTL Example – LED Load Analysis of the first circuit: + - 1.7 V I For this circuit, V out ≥2.4V and thus I ≥ 2mA > I OH ! (I OH = -0.4mA) This TTL logic device can’t supply this amount of current since the output voltage will decrease as the output current exceeds I OH. Thereby, a “1” state at the output is no longer guaranteed. ECE 3450 M. A. Jupina, VU, 2014

39. TTL Example – LED Load Analysis of the second circuit: I - + 1.7 V If V out = 0.4V, then I = 9 mA < I OL. ( I OL = 16 mA ) If V out = 0V, then I = 10 mA < I OL. The necessary output current can be supplied. For TTL, the magnitude of I OL > the magnitude of I OH ECE 3450 M. A. Jupina, VU, 2014

40. Fan-Out and Fan-In  Fan-out – number of load gates connected to the output of the driving gate l gates with large fan-out are slower N M  Fan-in – the number of inputs to the gate l gates with large fan-in are bigger and slower ECE 3450 M. A. Jupina, VU, 2014

41. Static or DC Fan-Out  Fan-Out (N) is defined as the number of loads (gate inputs) that can be driven by a single gate output at DC or low frequencies.  Low Level Fan-out N L =  High Level Fan-out N H =  N = min{N L,N H }  Ex: For most TTL families, N = N L. ECE 3450 M. A. Jupina, VU, 2014

42. TTL Static Fan-Out Example ECE 3450 M. A. Jupina, VU, 2014

43. Dynamic Fan-Out The impedance of a capacitor, (  C) -1, decreases as the frequency increases. Therefore, the load current increases as the frequency increases. This additional load current must be taken into account when determining fan-out at high frequency. Dynamic Fan-Out << Static Fan-Out Additional current due to the capacitive load. ECE 3450 M. A. Jupina, VU, 2014

44. Power Dissipation Definitions Instantaneous power: p(t) = v(t)i(t) = V supply i(t) Peak power: P peak = V supply i peak Average power: ECE 3450 M. A. Jupina, VU, 2014

45. Power Dissipation  Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates  power supply sizing (determined by peak power) P peak = V supply i peak –battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V supply i(t) P avg = 1/T  p(t) dt = V supply /T  i supply (t) dt –packaging and cooling requirements  Two important components: static (DC) and dynamic CMOS Example: P AV = V DD I leakage + C L V DD 2 f ECE 3450 M. A. Jupina, VU, 2014

46. TTL Supply Currents The power supply current is dependent on the output state. I CCL > I CCH since  I OL > I OH  I IL > I IH Note: these values are for a 7400 NAND Gate chip (total current for 4 NAND gates)

47. Power Dissipation of a TTL Gate ECE 3450 M. A. Jupina, VU, 2014

48. Power Dissipation of a TTL Gate Example What is the power dissipation of a single TTL NAND gate (7400)? ECE 3450 M. A. Jupina, VU, 2014

49. Power Supply Currents Versus Frequency 10 KHz 100 KHz 1 MHz 10 MHz 100 MHz ECE 3450 M. A. Jupina, VU, 2014

50. Propagation Delay Time A measure of how long it takes for a gate to change state. Ideally, should be as short as possible. t PHL - the time it takes the output to go from a high to a low t PLH - the time it takes the output to go from a low to a high Average Propagation Delay Time t p = V in V out ECE 3450 M. A. Jupina, VU, 2014

51. Modeling Propagation Delay Model circuit as a first-order RC network v in v out V out (t) = (1 – e –t/  )V,where  = RC Time to reach 50% point is t = ln(2)  = 0.69  t V0V0 C R ECE 3450 M. A. Jupina, VU, 2014

52. Modeling Propagation Delay Driver Gate and Load Gate are modeled as a first-order RC network R C vSvS v out +-+- v in Driver Load ECE 3450 M. A. Jupina, VU, 2014

53. CMOS Inverter as an Example pullup network pulldown network V DD V SS out in out + Drain ECE 3450 M. A. Jupina, VU, 2014

54. Switch Models of a CMOS Inverter V DD RnRn V out = 0 V in = V DD V DD RpRp V out = V DD V in = 0 ECE 3450 M. A. Jupina, VU, 2014

55. CMOS Inverter: Transient Response V out V R n R p V DD V V in V DD V in 0 (a) Low-to-high output(b) High-to-low output C L C L Capacitor Charging Capacitor Discharging ECE 3450 M. A. Jupina, VU, 2014

56. CMOS Inverter Propagation Delay Propagation delay is proportional to the time-constant of the network formed by the pull-down resistor or pull-up resistor and the load capacitance. t pHL = ln(2) R n C L = 0.69 R n C L t pLH = ln(2) R p C L = 0.69 R p C L t p = (t pHL + t pLH )/2 = 0.69 C L (R n + R p )/2 To equalize propagation delay times make the on- resistance of the NMOS and PMOS approximately equal. ECE 3450 M. A. Jupina, VU, 2014

57. PSPICE Simulation of Delay with RC Models (Switch) ECE 3450 M. A. Jupina, VU, 2014

58. The Effect of Fan-Out on Propagation Delay (b) Equivalent circuit for timing purposes x f (a) Inverter that drivesn other inverters To inputs of n other inverters To inputs of n other inverters C n x V out forn =1V out forn =4V out V DD Gnd Time0 (c) Propagation times for different values ofn ECE 3450 M. A. Jupina, VU, 2014

59. Measurement of the Average Propagation Delay Time under Loaded Conditions Ring Oscillator Circuit Note: This is a self-oscillating circuit that requires no signal input. 1 01 T = Period N = odd number of gates, t p = T/2N Typically, C L = 15pf or 50pF 010 ECE 3450 M. A. Jupina, VU, 2014

60. Maximum Frequency of Operation TTL Ex: t PLH = 22ns, t PHL = 15ns F max = 22 MHz ECE 3450 M. A. Jupina, VU, 2014

61. Propagation Delay and Power Dissipation (for a single gate) TTL { CMOS { TTL Comparison ECE 3450 M. A. Jupina, VU, 2014

62. Propagation Delay Versus Power Dissipation (for a single gate) Ideal ECE 3450 M. A. Jupina, VU, 2014

63. Power Dissipation and Propagation Delay Propagation delay and the power consumption of a gate are related Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate –the faster the energy transfer (higher power dissipation) the faster the gate For a given technology, the product of the power consumption and the propagation delay is a constant and is used as a bench- mark to compare digital technologies. –Power-Delay Product (PDP) specifies the energy consumed by the gate per switching event An ideal gate is one that is fast and consumes little energy and therefore the PDP should be as small as possible. ECE 3450 M. A. Jupina, VU, 2014

64. Power-Delay Product Calculation  The average power dissipation (mW) by a single gate is multiplied by the average propagation delay time (ns) of a single gate to get the total energy (pJ) dissipated by a gate for a given technology.  Compare the PDP of 4000 CMOS, ALS TTL, and ECL CMOS: PDP = (1mW) (100ns) = 100pJ ALS TTL: PDP = (1.5mW)( 4ns) = 6pJ ECL: PDP = (40mW) ( 1ns) = 40pJ ECE 3450 M. A. Jupina, VU, 2014

65. Common IC Packages ECE 3450 M. A. Jupina, VU, 2014

66. Comparison of Microprocessors in 2001 ECE 3450 M. A. Jupina, VU, 2014

67. How much space does a single MOS transistor occupy on a silicon chip? Example: 100 million transistors on a 1cm x 1cm Si die. 1 cm ~1  m L<0.1  m Source Drain Gate N N ~1  m ECE 3450 M. A. Jupina, VU, 2014

68. Moore’s Law in Microprocessors Transistors on lead microprocessors double every 2 years 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Courtesy, Intel Pentium ® IV ECE 3450 M. A. Jupina, VU, 2014

69. Intel 4004 Microprocessor 1971 2300 transistors 1 MHz clock ECE 3450 M. A. Jupina, VU, 2014

70. Intel Pentium (IV) Microprocessor 2001 42 million transistors 2 GHz clock ECE 3450 M. A. Jupina, VU, 2014

71. Evolution in DRAM Chip Capacity 1.6-2.4  m 1.0-1.2  m 0.7-0.8  m 0.5-0.6  m 0.35-0.4  m 0.18-0.25  m 0.13  m 0.1  m 0.07  m human memory human DNA encyclopedia 2 hrs CD audio 30 sec HDTV book page 4X growth every 3 years!

72. ECE 3450 M. A. Jupina, VU, 2014 Clock Frequency Lead microprocessors frequency doubles every 2 years Courtesy, Intel

73. Power Dissipation Lead Microprocessors power continues to increase Courtesy, Intel Power delivery and dissipation will be prohibitive ECE 3450 M. A. Jupina, VU, 2014

74. Power Density Power density too high to keep junctions at low temp Courtesy, Intel ECE 3450 M. A. Jupina, VU, 2014

75. Power Dissipation (Battery Lifetime) is an issue in all types of handhelds

76. ECE 3450 M. A. Jupina, VU, 2014 What is the Current Power Dissipation in Processors? For a group exercise in class, select a processor manufactured during the last three years and provide information on its power dissipation by specifying the thermal design power (TDP). TDP is the maximum amount of heat generated by the processor which the cooling system is required to dissipate. Look at processors manufactured by Intel, AMD, or Freescale and use the manufacturers’ web sites to obtain the information. Provide the website where you found your information. Specify the properties of the processors such as clock frequency, die size, number of transistors, and the number of cores (if applicable). Use the excel spreadsheet form at the course website to report your findings and email this file to your instructor when completed.