1. COM181 Computer Hardware Lecture 4: The MIPs CPU
"Adapted from Computer Organization and Design, 4th Edition, Patterson & Hennessy, © 2008.” This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders.
Also drawn from the work of Mary Jane Irwin ( )
You should read the MIPs handout after this lecture,
also we will revisit the MIP instruction set in tutorials and the next lecture
08/08/13

2. Assembly language High-level language e.g a = b + c;
Machine language e.g
Assembly language is between high-level and machine
Each statement defines one machine operation
Directly represents architecture
So if the hardware chip can’t multiply then there will be no multiply statement (you can multiply by successive addition!)
MIPs has very limited, simple, instructions.
It has 32 registers and can add, subtract, and, or, ex-or and shift
There is one instruction to move (copy) 32 bit data from memory to a register and one instruction to move(copy) 32 bit data to memory
(i.e you can’t just add the contents of a memory location to another – they have to be brought into registers to do the addition)
Assembler program translates to machine language
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3. INSTRUCTION SET ARCHITECTURES (ISA): Types
CISC: complex instruction set computer: Traditional computer architecture
Unique instructions for as many operations as possible
RISC: reduced instruction set computer: Look at actual instruction use, focus on most frequent ones
Advantages
Disadvantages
Each instruction can do more work
More complex hardware circuits
Programs use less memory
More expensive to develop and build
Easier to program directly or to write compilers
Usually slower
Advantages
Disadvantages
Easier to learn
Larger, more complex programs
Simpler circuits
Harder to program
Cheaper and more reliable to design and build
Depends on compiler for optimization
Faster, quicker to implement when foundry improves silicon processes
08/08/13

4. Stored program Stored program concept
Instructions and data are stored in the same memory
Instructions are simply another kind of data
Instructions are executed sequentially unless branch elsewhere or stop
Fetch-execute cycle
- Instruction fetch
Get the next instruction from memory
- Decode
Figure out what operation to perform on which operands
- Operand fetch
Get the operand values
- Execute
Perform the operation
- Store result
Repeat until done
08/08/13

5. Instructions
Any instruction set must perform a basic set of operations
May have more complex combinations or special operations as well
Types of operations
Data transfer: load, store
Arithmetic: add, subtract, multiply, divide
Logic: and, or, xor, complement
Compare: equal, not equal, greater than, less than
Branch/jump: change execution order
08/08/13

6. MIPS "Microcomputer without interlocked pipeline stages"
Name is pun on acronym for "millions of instructions per second"
RISC architecture developed in middle '80's
Extended through several versions - current: MIPS IV
Used in many "embedded" applications
Game machines: Sony, Nintendo
TV set top boxes: LSI Logic shipped 7 million in 2001
Routers: Cisco
Laser printers
PDAs
High-performance workstations: Silicon Graphics (Lord of the Rings, other films)
"Over 100 million sold"
08/08/13

7. MIPS: machine model notes
Main memory
data: 32-bit address: range from 0x to 0xFFFFFFFF (upper half of range reserved )
Processor
32 registers ($r0 to $r31, though $r0 is readonly and holds zero: these store data to perform operations to and from themselves - faster than main memory
load-store architecture: access memory only through load, store instructions
load: register <--- data from memory (ld instruction)
store: register ---> data to memory (sw instruction)
amount of data in bytes (1, 2, 4, 8) depends on instruction (we’ll stick to 32bit (4 time))
all other operations use only registers or immediate values (contained in instruction)
Design Principle #2: "Smaller is faster."
16 floating point registers (ignore these)
ALU: arithmetic-logic unit
performs operations on values in registers
control: determines how operations executed ("computer within computer")
08/08/13

8. MIPS: instructions
ALU performs arithmetic and logical operations (instructions)
Instruction specifies
1. The operation to perform.
2. The first operand (usually in a register).
3. The second operand (usually in a register).
4. The register that receives the result. (we call the MIPs a 3-address machine)
MIPS has about 111 different instructions (we will look at about a dozen)
all 32 bits, 3 different formats (r-type, i-type and j-type)
r-types all have three register addresses for 2,3 and 4 above
i-types have 2 registers and a 16bit constant (number).
j-type (there is only one instruction!) is a simple JUMP instruction, with a 26bit address built in to the 32 bit instruction.
08/08/13

9. MIPS: instruction example
Example: add unsigned
addu $r10,$r8,$r9 # add 2 numbers  this is assembler
Syntax
3-operand instructions: all arithmetic/logical operations
operands separated by commas. Design principle #1: "Simplicity favors regularity."
one operation per instruction, one instruction per line
operation: addu
registers
sources : $r8, $r9
target : $r10
comment: # add 2 numbers (Comments starts with #, ends with end of line)
Semantics
$r10 = $r8 + $r9; What humans understand
R[10] <-- R[8] + R[9] Alternative way of what
humans understand (RTL)
Machine code
hex: 0x
or in binary!
08/08/13

10. addu $r10,$r8,$r9 # add 2 numbers hex: 0x01095021 0 1 0 9 5 0 2 1
MIPS: instruction fields
R-types use three registers, their format is always the same. The 32 bits is split into 6 fields of varying lengths – 6 bit, then 4 x 5 bit then another 6 bit. (i-types have 4 fields, 6,5,5,16)
addu $r10,$r8,$r9 # add 2 numbers
hex: 0x
binary:
fields:
b b b b b b5-0
opcode $rs $rt $rd shamt function
R-types all have an opcode of six zeroes and the actual function code listed in the rightmost 6 bits. (i-types use the opcode field and have no function field)
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12. 08/08/13

13. 08/08/13

14. View from 30,000 Feet Diagram of MIPS – some parts not shown!!!
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15. The MIPs CPU is described in the textbook, note how the diagram below relates to lecture 3
PCSrc 1
ID/EX
EX/MEM
Control
IF/ID
Add
MEM/WB
Branch
Add 4
Shift
left 2
Instruction
Memory
Read Addr 1
Data
Memory
Register
File
Read
Data 1
Read Addr 2
Read
Address PC
Read
Data
Address 1
Write Addr
ALU
Read
Data 2 1
Write Data
Write Data
ALU
cntrl 16 32
Sign
Extend
EX/MEM.RegisterRd
MEM/WB.RegisterRd
IF/ID.RegisterRs
IF/ID.RegisterRt 1
Forward
Unit
08/08/13

16. A RISC machine has a limited number of addressing modes
Often you must deal with the management of complexity, and use abstraction and partition to reduce systems to sizes that the human brain can cope with...
When programming a MIPs CPU it is enough to maintain a “Programmer’s Model” of the CPU.
The CPU is designed as a RISC (Reduced Instruction Set Computer) machine, this suits implementing the hardware but not necessarily suits humans programming it!
Software tools help
A RISC machine has a fixed length instruction (32 bits in the simple MIPs)
A RISC machine has a limited number of addressing modes
A RISC machine has a limited number of operations (small instrucution set)
A RISC machine has, typically, a register bank and uses load/store instructions (only) to access main memory.
08/08/13

17. destination  source1 op source2
MIPs machines have three types of Instruction; R-type for arithmetic instructions – using Registers, I-type where the number needed is available immediately and J-type for conditional/control, jumps etc (there are also a few others...)
Example of some MIPS assembly language arithmetic statements
add $t0, $s1, $s2
sub $t0, $s1, $s2
Each arithmetic instruction performs only one operation
Each arithmetic instruction specifies exactly three operands
destination  source1 op source2
Operand order is fixed (the destination is specified first)
The operands are contained in the datapath’s register file ($t0, $s1, $s2)
The registers above have been given symbolic names, the actual numbered registers
Run from $0 to $31. We use software to convert the statements above to a 32 bit instruction. The ASSEMBLER program can also convert symbols into numbers
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18. MIPS Register File
Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file
Thirty-two 32-bit registers
Two read ports
One write port
Register File
src1 addr
src2 addr
dst addr
write data
32 bits
src1
data
src2 32
locations 5 32 5
25 = 5 32 32
Registers are
Fast
Smaller is faster & Make the common case fast
Easy for a compiler to use
e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order
Improves code density
Since register are named with fewer bits than a memory location
Register addresses are indicated by using $
For lecture
All machines (since 1975) have used general purpose registers
How many bits wide are each of the lines going into/out of the register file?
08/08/13

19. Naming Conventions for Registers
0 $zero constant 0 (Hdware)
1 $at reserved for assembler
2 $v0 expression evaluation &
3 $v1 function results
4 $a0 arguments
5 $a1
6 $a2
7 $a3
8 $t0 temporary: caller saves
(callee can clobber)
15 $t7
16 $s0 callee saves
(caller can clobber)
23 $s7
24 $t8 temporary (cont’d)
25 $t9
26 $k0 reserved for OS kernel
27 $k1
28 $gp pointer to global area
29 $sp stack pointer
30 $fp frame pointer
31 $ra return address (Hdware)
08/08/13

20. What about programs with lots of variables?
Registers vs. Memory
Arithmetic instructions operands must be in registers
only thirty-two registers are provided
Compiler associates variables with registers
What about programs with lots of variables?
Devices
Processor
Network
Control
Memory
Input
Datapath
Output
Store variables in memory!
So have to be able to move variables to/from memory and the register file easily
08/08/13

21. What about programs with lots of variables?
Registers vs. Memory
Arithmetic instructions operands must be in registers
only thirty-two registers are provided
Compiler associates variables with registers
Devices
Processor
Network
Control
Memory
Input
Datapath
Output
Store variables in memory!
So have to be able to move variables to/from memory and the register file easily
What about programs with lots of variables?
08/08/13

22. Processor – Memory Interconnections
Memory is a large, single-dimensional array
An address acts as the index into the memory array
Memory
read addr/
write addr
Processor ?
locations
read data
write data
For class handout 10
101 1
32 bits
08/08/13

23. Processor – Memory Interconnections
Memory is a large, single-dimensional array
An address acts as the index into the memory array
The word address of the data
Memory
read addr/
write addr 32
Processor ?
locations
read data 32
232 Bytes (4 GB)  230 Words (1 GW) 32
write data
For lecture
How many bits per line? 10 8
101 4 1
The data stored in the memory
32 bits
= 4 Bytes = 1 Word
08/08/13

24. Accessing Memory
MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)
lw $t0, 4($s3) #load word from memory
sw $t0, 8($s3) #store word to memory
The data transfer instruction must specify
where in memory to read from (load) or write to (store) – memory address
where in the register file to write to (load) or read from (store) – register destination (source)
The memory address is formed by summing the constant portion of the instruction and the contents of the second register
For class handout
What is the memory address of the given load and store instructions if $s3 contains the address 24?
08/08/13

25. Accessing Memory
MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)
lw $t0, 4($s3) #load word from memory
sw $t0, 8($s3) #store word to memory
The data transfer instruction must specify
where in memory to read from (load) or write to (store) – memory address
where in the register file to write to (load) or read from (store) – register destination (source)
The memory address is formed by summing the constant portion of the instruction and the contents of the second register 28 32
For lecture
What is the memory address of the given load and store instructions if $s3 contains the address 24?
08/08/13

26. Compiling with Loads and Stores
Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement
A[8] = A[2] - b
$s3
$s3+4
$s3+8
$s3+12
. . .
A[2]
A[3]
A[1]
A[0]
For class handout
08/08/13

27. Compiling with Loads and Stores
Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement
A[8] = A[2] - b
$s3
$s3+4
$s3+8
$s3+12
. . .
A[2]
A[3]
A[1]
A[0]
lw $t0, 8($s3)
sub $t0, $t0, $s2
sw $t0, 32($s3)
For lecture
lw $t0, 8($s3)
sub $t0, $t0, $s2
sw $t0, 32($s3)
08/08/13

28. Compiling with a Variable Array Index
Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement
c = A[i] - b
$s4
$s4+4
$s4+8
$s4+12
. . .
A[2]
A[3]
A[1]
A[0]
add $t1, $s3, $s3 #array index i is in $s3
add $t1, $t1, $t1 #temp reg $t1 holds 4*i
For class handout
08/08/13

29. Compiling with a Variable Array Index
Assuming that the base address of array A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement
c = A[i] - b
$s4
$s4+4
$s4+8
$s4+12
. . .
A[2]
A[3]
A[1]
A[0]
For class handout
add $t1, $s3, $s3 #array index i is in $s3
add $t1, $t1, $t1 #temp reg $t1 holds 4*i
add $t1, $t1, $s4 #addr of A[i] now in $t1
lw $t0, 0($t1)
sub $s2, $t0, $s1
08/08/13

30. Dealing with Constants
Small constants are used quite frequently (50% of operands in many common programs)
e.g., A = A + 5; B = B + 1; C = C - 18;
Solutions? Why not?
Put “typical constants” in memory and load them
Create hard-wired registers (like $zero) for constants like 1, 2, 4, 10, …
How do we make this work?
How do we Make the common case fast !
in gcc 52% of arithmetic operations involve constants – in spice its 69%
have he students answer why not – speed and limited number of registers
notice new instructions – bit wise and and bit wise or – requiring an ALU – talk a bit about how they work
08/08/13

31. Constant (or Immediate) Operands
Include constants inside arithmetic instructions
Much faster than if they have to be loaded from memory (they come in from memory with the instruction itself)
MIPS immediate instructions
addi $s3, $s3, 4 #$s3 = $s3 + 4
much faster than if loaded from memory
addi and slti does sign extend of immediate operand into the leftmost bits of the destination register (ie., copies the leftmost bit of the 16-bit immediate value into the upper 16 bits)
by contrast, ori and andi loads zero’s into the upper 16 bits and so is usually used (instead of the addi) to build 32 bit constants
There is no subi instruction, can you guess why not?
08/08/13

32. MIPS Instructions, so far
Category
Instr
Example
Meaning
Arithmetic
add
add $s1, $s2, $s3
$s1 = $s2 + $s3
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
add immediate
addi $s1, $s2, 4
$s1 = $s2 + 4
Data
transfer
load word
lw $s1, 32($s2)
$s1 = Memory($s2+32)
store word
sw $s1, 32($s2)
Memory($s2+32) = $s1
similarity of the binary representation of related instructions simplifies the hardware design
08/08/13

33. Machine Language - Arithmetic Instruction
Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
registers have numbers $t0=$8,$s1=$17,$s2=$18
Instruction Format:
Can you guess what the field names stand for?
op rs rt rd shamt funct
For class handout
08/08/13

34. Machine Language - Arithmetic Instruction
Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
registers have numbers $t0=$8,$s1=$17,$s2=$18
Instruction Format:
op rs rt rd shamt funct
For lecture
Can you guess what the field names stand for?
08/08/13

35. MIPS Instruction Fields
op rs rt rd shamt funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
= 32 bits op rs rt rd
shamt
funct
for class handout
08/08/13

36. MIPS Instruction Fields
op rs rt rd shamt funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
= 32 bits op rs rt rd
shamt
funct
opcode indicating operation to be performed
address of the first register source operand
address of the second register source operand
the register destination address
shift amount (for shift instructions)
for lecture
function code that selects the specific variant of the operation specified in the opcode field
08/08/13

37. Machine Language - Load Instruction
Consider the load-word and store-word instr’s
What would the regularity principle have us do?
But Good design demands compromise
Introduce a new type of instruction format
I-type for data transfer instructions (previous format was R-type for register)
Example: lw $t0, 24($s2)
Where's the compromise?
op rs rt bit number
For class handout
23hex
08/08/13

38. Machine Language - Load Instruction
Consider the load-word and store-word instr’s
What would the regularity principle have us do?
But Good design demands compromise
Introduce a new type of instruction format
I-type for data transfer instructions (previous format was R-type for register)
Example: lw $t0, 24($s2)
op rs rt bit number
For lecture
destination address no longer in the rd field - now in the rt field
offset limited to 16 bits - so can’t get to every location in memory (with a fixed base address)
23hex
Where's the compromise?
08/08/13

39. Memory Address Location
Example: lw $t0, 24($s2)
Memory
0xf f f f f f f f
$s2 = 0x 0x
$s2
For class handout
Note that the offset can be positive or negative
0x c 0x 0x 0x
data
word address (hex)
08/08/13

40. Memory Address Location
Example: lw $t0, 24($s2)
Memory
0xf f f f f f f f
$s2 =
$t0 0x
0x120040ac =
0x120040ac 0x
$s2
For lecture
What is the address of the memory location that gets loaded into $t0? … …
… = 0x020040ac
In SPIM, the code starts at 0x and the data area at 0x and the stack area at 0x7fff de00
Note that the offset can be positive or negative
0x c 0x 0x 0x
data
word address (hex)
08/08/13

41. Machine Language - Store Instruction
Example: sw $t0, 24($s2)
A 16-bit offset means access is limited to memory locations within a range of to (~8,192) words ( to (~32,768) bytes) of the address in the base register $s2
2’s complement (1 sign bit + 15 magnitude bits)
op rs rt bit number
For class handout
08/08/13

42. Machine Language - Store Instruction
Example: sw $t0, 24($s2)
A 16-bit offset means access is limited to memory locations within a range of to (~8,192) words ( to -215 (~32,768) bytes) of the address in the base register $s2
2’s complement (1 sign bit + 15 magnitude bits)
op rs rt bit number
For lecture
why is it 2**13 (2**15) and NOT 2**14 (2**16) like we just saw with memory (here we have to represent signed numbers so the most significant bit is the sign bit)
08/08/13

43. Machine Language – Immediate Instructions
What instruction format is used for the addi ? addi $s3, $s3, 4 #$s3 = $s3 + 4
Machine format:
For class handout
08/08/13

44. Machine Language – Immediate Instructions
What instruction format is used for the addi ? addi $s3, $s3, 4 #$s3 = $s3 + 4
Machine format:
op rs rt bit immediate
I format
The constant is kept inside the instruction itself!
So must use the I format – Immediate format
Limits immediate values to the range +215–1 to -215
For lecture
addi and slti does sign extend of immediate operand into the leftmost bits of the destination register (ie., copies the leftmost bit of the 16-bit immediate value into the upper 16 bits)
by contrast, ori and andi loads zero’s into the upper 16 bits and so is usually used (instead of the addi) to build 32 bit constants
08/08/13

45. Instruction Format Encoding
Can reduce the complexity with multiple formats by keeping them as similar as possible
First three fields are the same in R-type and I-type
Each format has a distinct set of values in the op field
Instr
Frmt op rs rt rd
shamt
funct
address
add R
reg
32ten NA
sub
34ten
addi I
8ten
constant lw
35ten sw
43ten

46. Assembling Code
Remember the assembler code we compiled last lecture for the C statement
A[8] = A[2] - b
lw $t0, 8($s3) #load A[2] into $t0
sub $t0, $t0, $s2 #subtract b from A[2]
sw $t0, 32($s3) #store result in A[8]
Assemble the MIPS object code for these three instructions (decimal is fine) lw
For class handout
sub sw
08/08/13

47. Assembling Code
Remember the assembler code we compiled last lecture for the C statement
A[8] = A[2] - b
lw $t0, 8($s3) #load A[2] into $t0
sub $t0, $t0, $s2 #subtract b from A[2]
sw $t0, 32($s3) #store result in A[8]
Assemble the MIPS object code for these three instructions (decimal is fine) 35 lw 19 8
For lecture lw
sub sw
sub 8 18 34 43 sw 19 8 32
08/08/13

48. Review: MIPS Instructions, so far
Category
Instr
Op Code
Example
Meaning
Arithmetic
(R format)
add
0 & 32
add $s1, $s2, $s3
$s1 = $s2 + $s3
subtract
0 & 34
sub $s1, $s2, $s3
$s1 = $s2 - $s3
(I format)
add immediate 8
addi $s1, $s2, 4
$s1 = $s2 + 4
Data
transfer
load word 35
lw $s1, 100($s2)
$s1 = Memory($s2+100)
store word 43
sw $s1, 100($s2)
Memory($s2+100) = $s1
similarity of the binary representation of related instructions simplifies the hardware design
08/08/13

49. MIPS Operand Addressing Modes Summary
Register addressing – operand is in a register
1. Register addressing
op rs rt rd funct
Register
word operand
Base (displacement) addressing – operand’s address in memory is the sum of a register and a 16-bit constant contained within the instruction
op rs rt offset
2. Base addressing
base register
Memory
word or byte operand
Immediate addressing – operand is a 16-bit constant contained within the instruction
3. Immediate addressing
op rs rt operand
08/08/13

50. MIPS Instruction Addressing Modes Summary
PC-relative addressing – instruction’s address in memory is the sum of the PC and a 16-bit constant contained within the instruction
4. PC-relative addressing
op rs rt offset
Program Counter (PC)
Memory
branch destination instruction
Pseudo-direct addressing – instruction’s address in memory is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC
5. Pseudo-direct addressing
op jump address
Program Counter (PC)
Memory
jump destination instruction ||
08/08/13

51. Review: MIPS Instructions, so far
Category
Instr
OpC
Example
Meaning
Arithmetic
(R & I format)
add
0 & 20
add $s1, $s2, $s3
$s1 = $s2 + $s3
subtract
0 & 22
sub $s1, $s2, $s3
$s1 = $s2 - $s3
add immediate 8
addi $s1, $s2, 4
$s1 = $s2 + 4
shift left logical
0 & 00
sll $s1, $s2, 4
$s1 = $s2 << 4
shift right logical
0 & 02
srl $s1, $s2, 4
$s1 = $s2 >> 4 (fill with zeros)
shift right arithmetic
0 & 03
sra $s1, $s2, 4
$s1 = $s2 >> 4 (fill with sign bit)
and
0 & 24
and $s1, $s2, $s3
$s1 = $s2 & $s3 or
0 & 25
or $s1, $s2, $s3
$s1 = $s2 | $s3
nor
0 & 27
nor $s1, $s2, $s3
$s1 = not ($s2 | $s3)
and immediate c
and $s1, $s2, ff00
$s1 = $s2 & 0xff00
or immediate d
or $s1, $s2, ff00
$s1 = $s2 | 0xff00
load upper immediate f
lui $s1, 0xffff
$s1 = 0xffff0000
08/08/13

52. Review: MIPS Instructions, so far
Category
Instr
OpC
Example
Meaning
Data
transfer
(I format)
load word 23
lw $s1, 100($s2)
$s1 = Memory($s2+100)
store word 2b
sw $s1, 100($s2)
Memory($s2+100) = $s1
load byte 20
lb $s1, 101($s2)
$s1 = Memory($s2+101)
store byte 28
sb $s1, 101($s2)
Memory($s2+101) = $s1
load half 21
lh $s1, 101($s2)
$s1 = Memory($s2+102)
store half 29
sh $s1, 101($s2)
Memory($s2+102) = $s1
Cond. branch
(I & R format)
br on equal 4
beq $s1, $s2, L
if ($s1==$s2) go to L
br on not equal 5
bne $s1, $s2, L
if ($s1 !=$s2) go to L
set on less than immediate a
slti $s1, $s2, 100
if ($s2<100) $s1=1; else $s1=0
set on less than
0 & 2a
slt $s1, $s2, $s3
if ($s2<$s3) $s1=1; else $s1=0
Uncond. jump
jump 2 j
go to 10000
jump register
0 & 08
jr $t1
go to $t1
jump and link 3
jal
go to 10000; $ra=PC+4
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53. Review: MIPS R3000 ISA Instruction Categories
Load/Store
Computational
Jump and Branch
Floating Point
coprocessor
Memory Management
Special
3 Instruction Formats: all 32 bits wide
Registers
R0 - R31 PC HI LO
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
R format OP rs rt rd
shamt
funct
I format OP rs rt
16 bit number
J format OP
26 bit jump target
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54. RISC Design Principles Review
Simplicity favors regularity
fixed size instructions – 32-bits
small number of instruction formats
Smaller is faster
limited instruction set
limited number of registers in register file
limited number of addressing modes
Good design demands good compromises
three instruction formats
Make the common case fast
arithmetic operands from the register file (load-store machine)
allow instructions to contain immediate operands
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55. The Code Translation Hierarchy
C program
compiler
assembly code
Four logical phases all programs go through
C code – x.c or .TXT
assembly code – x.s or .ASM
object code – x.o or .OBJ
executable – a.out or .EXE
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56. Compiler Transforms the C program into an assembly language program
Advantages of high-level languages
many fewer lines of code
easier to understand and debug …
Today’s optimizing compilers can produce assembly code nearly as good as an assembly language programming expert and often better for large programs
smaller code size, faster execution
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57. The Code Translation Hierarchy
C program
compiler
assembly code
assembler
object code
Four logical phases all programs go through
C code – x.c or .TXT
assembly code – x.s or .ASM
object code – x.o or .OBJ
executable – a.out or .EXE
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58. Assembler
Does a syntactic check of the code (i.e., did you type it in correctly) and then transforms the symbolic assembler code into object (machine) code
Advantages of assembler
much easier than remembering instr’s binary codes
can use labels for addresses – and let the assembler do the arithmetic
can use pseudo-instructions
e.g., “move $t0, $t1” exists only in assembler (would be implemented using “add $t0,$t1,$zero”)
When considering performance, you should count instructions executed, not code size
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59. The Two Main Tasks of the Assembler
Builds a symbol table which holds the symbolic names (labels) and their corresponding addresses
A label is local if it is used only within the file where its defined. Labels are local by default.
A label is external (global) if it refers to code or data in another file or if it is referenced from another file. Global labels must be explicitly declared global (e.g., .globl main)
Translates each assembly language statement into object (machine) code by “assembling” the numeric equivalents of the opcodes, register specifiers, shift amounts, and jump/branch targets/offsets
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60. MIPS (spim) Memory Allocation
f f f f f f f c
Mem Map I/O
Kernel Code & Data
$sp
7f f f f f fc
Stack
230
words
Dynamic data
$gp
Static data
Note that stack grows down into dynamic data area.
Text
Segment PC
Reserved
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61. Other Tasks of the Assembler
Converts pseudo-instr’s to legal assembly code
register $at is reserved for the assembler to do this
Converts branches to far away locations into a branch followed by a jump
Converts instructions with large immediates into a lui followed by an ori
Converts numbers specified in decimal and hexidecimal into their binary equivalents and characters into their ASCII equivalents
Deals with data layout directives (e.g., .asciiz)
Expands macros (frequently used sequences of instructions)
Unlike subroutines (which invoke calls and returns) the macro call is replaced by the macro body when the program is assembled
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62. Typical Object File Pieces
Object file header: size and position of the following pieces of the file
Text (code) segment (.text) : assembled object (machine) code
Data segment (.data) : data accompanying the code
static data - allocated throughout the program
dynamic data - grows and shrinks as needed
Relocation information: identifies instructions (data) that use (are located at) absolute addresses – not relative to a register (including the PC)
on MIPS only j, jal, and some loads and stores (e.g., lw $t1, 100($zero) ) use absolute addresses
Symbol table: global labels with their addresses (if defined in this code segment) or without (if defined external to this code segment)
Debugging information
text segments may be unexecutable because of unresolved references (to be fixed by the linker-loader)
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63. An Example Gbl? Symbol Address Relocation Info Address Data/Instr str cr b
yes
main
loop c
brnc c
done
printf
???? ????
.data
.align 0
str: .asciiz "The answer is "
cr: .asciiz "\n"
.text
.align 2
.globl main
.globl printf
main: ori $2, $0, 5
syscall
move $8, $2
loop: beq $8, $9, done
blt $8, $9, brnc
sub $8, $8, $9
j loop
brnc: sub $9, $9, $8
done: jal printf
Relocation Info
Address
Data/Instr
str b cr
j loop
jal printf

64. The Code Translation Hierarchy
C program
compiler
assembly code
main text segment
assembler
object code
printf text segment
library routines
executable
linker
Four logical phases all programs go through
C code – x.c or .TXT
assembly code – x.s or .ASM
object code – x.o or .OBJ
executable – a.out or .EXE
machine code
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65. Linker
Takes all of the independently assembled code segments and “stitches” (links) them together
Faster to recompile and reassemble a patched segment, than it is to recompile and reassemble the entire program
Decides on memory allocation pattern for the code and data segments of each module
Remember, modules were assembled in isolation so each has assumed its code’s starting location is 0x and its static data starting location is 0x
Relocates absolute addresses to reflect the new starting location of the code segment and its data segment
Uses the symbol tables information to resolve all remaining undefined labels
branches, jumps, and data addresses to/in external modules
Linker produces an executable file
File has same format as object file output by assembler - except it contains no unresolved reference, relocation information, symbol table, or debugging information
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66. Linker Code Schematic Linker Executable file Object file C library
main: .
jal printf
printf:
Executable file
Object file
main: .
jal ????
call, printf
Linker
C library
printf: .
Relocation info
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67. Linking Two Object Files
Executable
File 1 +
File 2
Hdr Txtseg Dseg Reloc
Hdr Txtseg Dseg Reloc Smtbl Dbg
Hdr Txtseg Dseg Reloc Smtbl Dbg
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68. The Code Translation Hierarchy
C program
compiler
assembly code
assembler
object code
library routines
executable
linker
Four logical phases all programs go through
C code – x.c or .TXT
assembly code – x.s or .ASM
object code – x.o or .OBJ
executable – a.out or .EXE
machine code
loader
memory
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69. Loader
Loads (copies) the executable code now stored on disk into memory at the starting address specified by the operating system
Copies the parameters (if any) to the main routine onto the stack
Initializes the machine registers and sets the stack pointer to the first free location (0x7fff fffc)
Jumps to a start-up routine (at PC addr 0x on xspim) that copies the parameters into the argument registers and then calls the main routine of the program with a jal main
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70. Dynamically Linked Libraries
Statically linking libraries mean that the library becomes part of the executable code
It loads the whole library even if only a small part is used (e.g., standard C library is 2.5 MB)
What if a new version of the library is released ?
(Lazy) dynamically linked libraries (DLL) – library routines are not linked and loaded until a routine is called during execution
The first time the library routine called, a dynamic linker-loader must
find the desired routine, remap it, and “link” it to the calling routine (see book for more details)
DLLs require extra space for dynamic linking information, but do not require the whole library to be copied or linked
New releases fix bugs, support new hardware devices, …
Lazy DLLs also pay overhead the first time a routine is called (to do the linking), but only a single indirect jump thereafter. The return from the library pays no extra overhead.
Microsoft Windows relies extensively on lazy dynamically linked libraries, and it is also the normal way of executing programs on UNIX
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71. 08/08/13