1. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 1 Phase 2 Architecture Options Oliver Buchmueller Imperial College Wesley H. Smith U. Wisconsin Trigger Performance & Strategy Working Group Report Upgrade Project Office Meeting July 5, 2012 Outline: Status/Plans Discussion on Readout Options

2. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 2 Status/PlansStatus/Plans Friday, June 29: Survey of Sub-detector readout, trigger & DAQ requirements and constraints Examine the envelope within which we can design Input to decision about CMS architecture for HL-LHC detector – finalize by end of year. Summary provided in this talk Agenda included talks from sub-detectors and DAQ Wednesday, July 25: Dedicated meeting with Physics about goals and requirements for triggering in the HL-LHC Survey initial results from physics groups and develop plan of work for subsequent studies. Thursday, July 26: Follow-up meeting on Phase 2 Architecture Get more details, answer further questions from previous meeting: ECAL details, Computing…

3. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 3 Phase 2 CMS Level-1 Latency? Present CMS Latency of 4.0 μsec = 160 crossings @ 40MHz Limitation from post-L1 buffer size of tracker & preshower Assume rebuild of tracking & preshower electronics will store more than this number of samples Do we need more? Not all crossings used for trigger processing It’s the cables! How much more? Justification? Combination with tracking logic Increased algorithm complexity Asynchronous links or FPGA-integrated deserialization require more latency Finer result granularity may require more processing time ECAL digital pipeline memory is 256 40 MHz samples = 6.4 μsec Next option for an increase (use 6.0 μsec)

4. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 4 CMS Readout Options Read out all detectors after 6 μsec at L1 rate Pro: Don’t need to rebuild ECAL FE Con: Still have subset of calorimeter & muon detector information used to triggering Read out calorimeter & muon detectors in real time at 40 MHz, tracker at L1 rate after L1 latency Pro: Do have to rebuild ECAL FE Pro: Have all muon & calorimeter information available for L1 Trigger Decision Pro: Can increase latency to limit of buffering of tracker data Pro: Can increase L1 Trigger Rate to limit of tracker readout power (100 → 200 → 500 kHz) Con: Need to rebuild all FE electronics Intermediate situation Still have to rebuild all FEE but only have partial calorimeter and muon trigger information at L1.

5. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 5 Questions to Subsystems What are the limitations on the level-1 trigger latency of your subsystem? What would be required at what cost and effort (just order of magnitude) to increase the latency to 6, 10 or 20 usec. What are the limitations on the level-1 trigger rate of your subsystem? What would be required at what cost and effort (just order of magnitude) to increase this rate to 200 kHz or 500 kHz or 1 MHz or full readout of your subsystem at the crossing frequency of 40 MHz? For both of these questions, please provide some information on the source of the limitations (power, need to rebuild electronics, space, fibers, etc.) We are also interested to know what data volume we might expect from your detector after LS3.

6. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 6 Input from DAQ, Tracker DAQ assuming 10 MB event size: Readout at 100 kHz, 1 MHz no problem, HLT OK Readout at 40 MHz very difficult, HLT too high cost Output at 1 kHz OK. Need to check max w/Computing Tracker assumes no EB rebuild: Latency within 6.4 µs, L1A at 100 kHz If EB rebuilt, option for readout up to 1 MHz Tracking Trigger, p T > 2-2.5 GeV, “push path” Lower bandwidth of data out → lower power Phase 2 Pixel readout based on RoI possible, design just starting Phase 2 Pixel trigger is on the table

7. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 7 Input from Calorimeters ECAL assuming 100 kHz L1A: EB pipeline absolute maximum depth is 6.4 µsec DCC readout designed for 2kB/100kHz/10 samples Trigger Boards tested to 150 kHz w/random data 200 kHz L1A means readout 8 → 5 usec (only 4 samples) ES pipeline depth presently 4.8 µsec (assume is gone?) DCC max 120 kHz, detector max 100 kHz Major issue is rebuild of EB FEE HCAL: Latency of 20 – 40 µsec no problem Need to replace HO VME electronics for Phase 2 ($150K) 250 kHz L1A achievable, 1 MHz probably out of reach Some options for AMC13 replacement to be looked at

8. O. Buchmueller, Imperial College, W. Smith, U. Wisconsin, UPO Meeting, July 6, 2012 Trigger Performance and Strategy Working Group Trigger Performance and Strategy Working Group - 8 Input from Muon Systems RPC: Higher L1A rate or latency requires new RMB, DCC & more/higher bandwidth optical links DT: On-detector ROB HPTDCs accept L1A up to 25 µsec Replacing ROB’s major effort Higher L1A rate or latency requires new ROS Readout Server Boards will be in USC, planned redesign once DDU limit is 250 MB/s (1 kB/evt x 250 kHz L1A) Question of data volume – double the FEDs? ROB output link BW limited to L1A < 800 kHz Full readout at 40 MHz does not work (BCID) CSC: Full readout at 40 MHz does not work (5.7 MB/bx) Local Chg. Trk Trig. (ALCT&CLCT) & L1A required to readout CFEB SCA bottleneck 3.2 µsec L1A latency + CLCT rate (poisson statistics) 26 µsec digitization + L1A rate (queue statistics) DCFEB not restricted Only planned for ME1/1 – cost for all CSCs = 12 M$ Data Volume: presently 5.5 kb → 18 kb/CSC @ 100 vertices – needs study