1. 1 Introduction to Time Dependent Dielectric Breakdown in Digital Circuits Traps generated under the influence of electric field Gate dielectric no longer a reliable insulator Statistical process requires large # of tests for characterization Stressed NMOS Cross Section Breakdown in Digital Circuits Time-to-Breakdown CDFs

2. 2 An Array-Based Test Circuit for Fully Automated TDDB Characterization Measure 32x32 array of stressed transistors in parallel without a probe station 16b results scanned out and stored for post-processing Efficient collection of failure statistics by running a simple control program Wafer Probe Station Proposed System Save: (1) Time (2) $$$$

3. 3 Measured T BD Results Array-based design  define a CDF with a single test and check spatial correlation Parallel stressing  large experiment speedup Cheap & accessible test setup Fast Statistical Characterization Analysis of Spatial Correlation Measurement Lab Setup