1. Speedstack: PCB Stack Up Data Exchange Using IPC-2581 Rev B
March 2014 Rev 4 – Michael Bode / Richard Attrill
Copyright © 2014 Polar Instruments, Inc. and Cadence Design Systems, Inc.

2. Introduction to IPC-2581
An efficient data exchange format to be used between designers and manufacturers of printed circuit boards
A replacement for the multiple Gerber, NC Drill, Net List, Stack Up and Documentation files normally included within a data set that a designer sends for fabrication and assembly
A single file rather than multiple files
Uses industry-standard XML format

3. Overview

4. IPC-2581 Consortium Members

5. Why change from existing data formats?
Gerber is a proven format, but it really does not have the intelligence customers need today to communicate design data to manufacturing
It lacks stack up details
It lacks net list information
It lacks other data such as bill of materials and manufacturing notes

6. Versions
IPC-2581 Original Release – March 2004 (yes, 2004 !)
IPC-2581 Rev 1 – May 2007
IPC-2581 Rev A – May 2012
IPC-2581 Rev B – September 2013
Many enhancements introduced with IPC-2581 Rev B including a the ability to comprehensively define the stack up requirement

7. Workflow Pre-layout stack up design PCB layout system
IPC-2581
Pre-layout stack up design
PCB layout system
IPC-2581
Fabricator final stack up design

8. Pre-layout stack up design
Pre-layout stack up designs often use ‘Virtual Materials’, where the design engineer specifies copper / substrate thicknesses but not the actual fabrication materials used.
Once the stack arrives at the Fabricator these ‘Virtual Materials’ are exchanged for the true materials.

9. Pre-layout stack up design
The finished copper thickness and final substrate heights are critical for impedance calculations.
A single dielectric substrate region could be constructed from multiple materials in order to manufacture the required height.

10. Stack up technical report
Reports are created once the stack is completed.

11. Export stack up to IPC-2581 format
The completed stack is exported to
IPC-2581 so that it can be imported into the other PCB design tools such as Cadence Allegro
IPC-2581

12. IPC-2581 XML – Layer section
<Layer name="SOLDERMASK_TOP" layerFunction="SOLDERMASK" side="TOP" polarity="POSITIVE" />
<Layer name="L1" layerFunction="SIGNAL" side="TOP" polarity="POSITIVE“ />
<Layer name="DIELECTRIC_1" layerFunction="DIELPREG" side="INTERNAL" polarity="POSITIVE“ />
<Layer name="L2" layerFunction="PLANE" side="INTERNAL" polarity="NEGATIVE“ /> ….
<Layer name="L6" layerFunction=“SIGNAL" side="INTERNAL" polarity=“POSITIVE“ />
<Layer name="DIELECTRIC_4" layerFunction="DIELCORE" side="INTERNAL" polarity="POSITIVE“ />
<Layer name="L7" layerFunction="PLANE" side="INTERNAL" polarity="NEGATIVE“ />
<Layer name="L7" layerFunction="PLANE" side="INTERNAL" polarity="NEGATIVE“ />

13. IPC-2581 XML – Stack Up section
<Stackup overallThickness=" " tolPlus="0.0050" tolMinus="0.0050" whereMeasured="METAL">
<StackupGroup name="AllStackupLayers" thickness=" " tolPlus="0.0050" tolMinus="0.0050">
<StackupLayer layerOrGroupRef="SOLDERMASK_TOP" thickness="0.0010" sequence="1">
<SpecRef id="SOLDERMASK_TOP_SPEC"/>
</StackupLayer>
<StackupLayer layerOrGroupRef="L1" thickness=" " sequence="2">
<SpecRef id="L1_SPEC"/>
<StackupLayer layerOrGroupRef="DIELECTRIC_1" thickness="0.0030" sequence="3">
<SpecRef id="DIELECTRIC_1_SPEC"/> …
<StackupLayer layerOrGroupRef="L6" thickness=" " sequence="12">
<SpecRef id="L6_SPEC"/>
<StackupLayer layerOrGroupRef="DIELECTRIC_5" thickness="0.0050" sequence="13">
<SpecRef id="DIELECTRIC_5_SPEC"/>
<StackupLayer layerOrGroupRef="L7" thickness=" " sequence="14">
<SpecRef id="L7_SPEC"/>
SpecRef id. Each material within the stack up has a Specification Reference id that points to a material specification. This specification contains material properties such as Dielectric Constant
<StackupLayer layerOrGroupRef="L7" thickness=" " sequence="14">
<SpecRef id="L7_SPEC"/>
</StackupLayer>

14. IPC-2581 XML – Specification section
<StackupLayer layerOrGroupRef="DIELECTRIC_1" thickness="0.0030" sequence="3">
<SpecRef id="DIELECTRIC_1_SPEC"/>
</StackupLayer>
<Spec name="DIELECTRIC_1_SPEC">
<General type="MATERIAL">
<Property text="Dielectric"/>
</General>
<Dielectric type="DIELECTRIC_CONSTANT">
<Property value="4.2000"/>
</Dielectric>
<Dielectric type="LOSS_TANGENT">
<Property value="0.0350"/>
<Dielectric type="RESIN_CONTENT">
<Property value=" " unit="PERCENT"/>
</Spec>
Specification section. These are the properties for the specific dielectric material within the stack up

15. Speedstack to Cadence Allegro interface using IPC-2581 format

16. Cadence Allegro Layout Cross Section

17. Fabricator final stack up design – exchange Virtual Materials
On receipt of the stack, the fabricator exchanges the ‘Virtual Materials’ for real PCB materials.

18. Fabricator final stack up design – exchange Virtual Materials
In this case, a single dielectric substrate region of 14 mils is constructed from 3 sheets of materials in order to manufacture the required height.
It is not possible to exactly manufacture 14 mils, the nearest manufacturable height is mils ( ).

19. Fabricator final stack up design – final checks
Stack up is checked to ensure that the final fabrication stack up still meets the required design specification.

20. Export final fabrication stack up to IPC-2581 format
It is often useful to pass the final fabrication stack “back up the chain” so that future designs can make use of accurate fabrication data.
IPC-2581

21. Speedstack to Cadence Allegro interface using IPC-2581 format

22. Cadence Allegro Layout Cross Section

23. Summary of using IPC-2581 format for stack up data exchange
A comprehensive, single file data format
Allows for the exchange of data between designers and fabricators
Supported by a growing consortium of software vendors and users
Polar will be releasing a version of Speedstack with export to IPC-2581 capability at the end of March, 2014.
For more information:

24. Thank you
Copyright © 2014 Polar Instruments, Inc. and Cadence Design Systems, Inc.