1. Roadmap of Microelectronic Industry

2. Scaling of MOSFET Reduction of channel length L  L/α Integration density  α 2 Speed  α; Power/device  1/α 2 Power density unchanged; Voltage  1/α Equivalent thickness of gate oxide  1/ 

3. Gate Dielectric film in ULSI MOSFET p-Si n+ Gate Gate oxide

4. Equivalent Gate Oxide Thickness t Eq = t x  SiO2 /  x  x: dielectric constant of insulator X  SiO2 = 3.2 Use high-  x insulator

5. Possible epitaxial dielectric films on Si rr On Si(100) (rectangular) On Si(111) (triangular) Si 3 N 4 6-9 amorphousHex., a = 7.6 Å, mismatch 1%, 900°C  -Al 2 O 3 9 Cubic, a = 7.91Å mismatch 3.5%, 800°C Same as on (100) CeO 2 26 Cubic, a = 5.45 Å mismatch 0.4%, < 550°C Same as on (100) ZrO 2 (Y-stb) 25 Cubic, a ~ 5.2 Å mismatch 3%, 730°C ? HfO 2 25 Amorphous

6. Metallization target parameters (current)

7. Electromigration Effects Void Pile-up Electron wind and field-driven atomic migration

8. Lower levels: fine connections to individual devices Upper levels: thicker/wider common connections Cu metallization: reducing wire resistance Low-k dielectrics: reducing parasitic capacitance RC delay issue Multi-level Metallization

9. Lithography: shorter wavelength (deep UV, X-ray, electron/ion beams) source, optics, resist materials Gate insulator: with high dielectric constant (high-k), high dielectric strength, effective barrier to impurity (e.g., B) migration Si-on-insulator (SOI): reducing capacitive coupling between devices, power consumption, effective heat dissipation

10. Double-gate FET Double-gate FET by selective epitaxial growth

11. Single-electron Tunneling (SET) Transistor Coulomb blockade effect Devices based on quantum effects in nano- structured materials quantum dots/wire, nano-wires (e.g., carbon nanotubes), molecular devices, …

12. Index of Single-wall Carbon Nanotubes (SWNT) Armchair (n, n) Zigzag (n, 0) General (m, n)

13. Electronic properties of SWNTs SWNTs: 1D crystal If m - n = 3q  metallic Otherwise  semiconductor Zigzag, d t = 1.6nm  =18 , d t = 1.7nm  =21 , d t = 1.5nm  =11 , d t = 1.8nm Armchair, d t = 1.4nm STM I-V spectroscopy Bandgap of semiconducting SWNTs: = 1.42 Å,  5.4 eV, overlap integral

14. Doping of semiconductor SWNTs N, K atoms  n-type; B atoms, oxygen  p-type SWNT CMOS inverter & its characteristics SWNT Transistors

15. Molecular diodes and nonlinear devices Molecule with D-  -A structure C 16 H 33 Q-3CNQ Highly conductive zwitterionic D + -  -A - state at 1-2V forward bias Reverse conduction state D - -  -A + requires bias of 9V I-V curve of Al/4-ML C 16 H 33 Q-3CNQ LB film/Al structure A  D

16. Ultimate Physical Limits Thermodynamic limit: energy consumption in handling 1 bit of information = kT log 2  18 meV = 3  10 -21 J at RT Current products: Pentium 4, power consumption 30 W, consists > 2.5  10 6 devices operating at > 4  10 8 Hz, energy cost per bit of operation  10 -15 J Demonstrated in laboratory: energy cost of operating a single- molecule switch is ~ 10 -19 J

17. Real Materials and their Processing  Particles, lines and rigid bodies vs. real materials: each material has its own characteristics  Material-specific properties determine the function and processing details of a material  Comprehensive knowledge of materials processing requires ~ 5-10 years of learning and practice: Interdisciplinary between physics, chemistry, electronics, materials science, economics…  Advantage and role of physicist

18. Graduate Attributes (Southern Cross University, Australia) Intellectual rigour Creativity Ethical understanding, sensitivity, commitment Command an area of knowledge Lifelong learning --- ability of independent & self- directed learning Effective communication and social skills Cultural awareness (From: S. Yeo, CDTLink, NUS, July 2004)

19. Final Exam  24 Nov, two hours  One A4 cheat sheet allowed, both sides  What will be in the exam? Basic principle, processes…, mainly after Chapter 5