1. The Impact of Variability on the Reliability of Long on-chip Interconnect in the Presence of Crosstalk Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alex Yakovlev, Gordon Russell Newcastle University UK

2. Outline Structure and fabrications of Modern Interconnect Why are two nominally identical wires different ? Impact of variability on Wire Delay and Crosstalk Glitches What are the Failure Mechanism in Capacitance-Dominated links ? Does Variability make things worse ? Conclusions

3. Interconnect Stack in Modern Technologies Source : ITRS 2007

4. 1. Start with the previous interlayer dielectric How to Build Multilayer's Interconnect Structure

5. 2. Add an ‘etch stop' layer How to Build Multilayer's Interconnect Structure

6. 3. Add a new layer of intra-layer dielectric How to Build Multilayer's Interconnect Structure

7. 4. Etch spots in the dielectric for wires How to Build Multilayer's Interconnect Structure

8. 5. Deposit the barrier metal How to Build Multilayer's Interconnect Structure

9. 6. Deposit the metal How to Build Multilayer's Interconnect Structure

10. 7. Grind it flat How to Build Multilayer's Interconnect Structure

11. 8. Add a dielectric cap/via etch stop How to Build Multilayer's Interconnect Structure

12. 9. Add more inter-layer insulator How to Build Multilayer's Interconnect Structure

13. 10. Add another etch stop How to Build Multilayer's Interconnect Structure

14. 11. Cut holes in dielectric for the vias How to Build Multilayer's Interconnect Structure

15. 12. Cut holes in each stop layer for the vias How to Build Multilayer's Interconnect Structure

16. 13. Deposit via metal How to Build Multilayer's Interconnect Structure

17. Interconnect Stack in Modern Technologies 14. Repeat the process for more layers

18. Variability Sources Fabrication Process Lithography – exact size and shape depend on environment Etching – also depends on environment Thickness of metal depends on CMP environment Deposition and polishing steps depend on chip location on the wafer Alignment between layers can affect vias Source (An Overview of On-chip Interconnect Variation Lou Scheffer, SLIP 2006 ) Environmental Factors power supply and temperature Other Factors an example of a statistical variation that results in deterministic uncertainty : CMP etching as function of location on a wafer

19. Variability Impact on wire electric parameters Normalized wire capacitance distribution (C) Normalized metal resistance across manufacturing lines (R) Source: Statistical Analysis and Optimization in the Presence of Gate and Interconnect Delay Variations Chandu Visweswariah,IBM,SLIP 2006

20. Motivations In DSM regime, due to process scaling, the contribution of interconnect delay has become significant Wire delay and coupling effects play a significant role in determining ultimate performance not easy to predict which is the worst corner

21. This work … Identify Interconnect Parametric Variations Develop a model for (Dwire,, GAmplitude) Statistical Analysis to Compute BER Identify the Impact of Variability Compare Different Design Approaches

22. Wire Model

23. Variations ParameterNominal ValueVariations Dielectric height (h)9.40E-07 m 20% Wire resistivity (ρ)2.18E-08 Ωm 20% Wire thickness (t)8.10E-07 m 20% Wire Width (w)5.60E-07 m 20% Transistor length (Leff)90 nm10% Power Supply (Vdd)1.2 V10% Temperature (temp)27 o C12 – 43 o C

24. Delay Sensitivity to Variability Sources Un-Buffered Line (L=10mm, K=1) Uniformly Buffered Line (L=10mm,K=4)

25. Crosstalk Glitches Sensitivity to Variability Sources Un-Buffered Line (L=10mm, K=1)

26. The Impact of Switching Activity Crosstalk CaseTransitionsTotal Capacitance 1↑↑↑, ↓↓↓Cg 2↑↑-,↓↓-, -↑↑, -↓↓Cg +Cc 3-↑-, -↓-, ↓↑↑, ↑↓↓, ↑↑↓, ↓↓↑, Cg +2Cc 4↓↑-, -↓↑, -↑↓, ↑↓-Cg +3Cc 5↓↑↓, ↑↓↑Cg +4Cc

27. Delay Sensitivity to Variability Sources Un-Buffered Line (L=10mm, K=1)

28. This work … Identify Interconnect Parametric Variations Develop a model for (Dwire,, GAmplitude) Statistical Analysis to Compute BER Identify the Impact of Variability Compare Different Design Approaches

29. Failure Mechanism in Capacitive Coupled Links Timing Failure This undesired effects occurs when the timing of a stage becomes uncertain due to coupling from the switching activity of neighboring stages, which results in a change in the total capacitance of the wire, hence dynamic delay. Functional Failure which is caused by static noise, induced on a quiet victim net due to switching of neighboring aggressors.

30. Interconnect States StateTransitionsFailure Mechanism D0↑↑↑, ↓↓↓Timing Failure D10↑↑, ↑↑0, 0↓↓, ↓↓0,1↑↑, ↑↑1, 1↓↓, ↓↓1 Timing Failure D2↓↑↑,↑↑↓,↓↓↑,↑↓↓,0↑0,0↓0,1↓1,1↑1, 1↑0,1↓0,0↑1,0↑1 Timing Failure D31↑↓,0↑↓,↓↑1,↓↑0,1↓↑,0↓↑,↑↓1,↑↓0Timing Failure D4↓↑↓,↑↓↑Timing Failure G0000,001,010,011,100,101,110,111, ↓00,00↓,↓01,10↓, 11↑,↑11,01↑,↑10,↓0↓,↑1↑ None G1↑0↓, ↑1↓,↓0↑,↓1↑Functional Failure G2↑00,↑01,00↑,10↑,↓11,↓10,01↓,11↓Functional Failure G3↑0↑,↓1↓Functional Failure

31. BER Analysis PE =-0.5- Q PE = (D wire >T clk - T setup ) Timing Failure : μ θ = μ D + μ Tsetup – μ Tclk σ 2 θ = σ 2 D + σ 2 Tsetup +σ 2 Tclk

32. BER Analysis PE =-0.5- Q PE = Pr (Amp > Vth) μ χ = μ Amp – μ Vth σ 2 χ = σ 2 Amp +σ 2 Vth Functional Failure:

33. BER Analysis BER = P: is the Error Rate in each state O: is the probability of Occurrence of each state

34. This work … Identify Interconnect Parametric Variations Develop a model for (Dwire,, GAmplitude) Statistical Analysis to Compute BER Identify the Impact of Variability Compare Different Design Approaches

35. Variability: Good or Bad ?

36. How to combat variability ?

38. Conclusions Novel bit error rate estimation method Mathematical expressions - quick tool to compare different design approaches. BER model developed for self-timed interconnect links Future directions - quantifying the variability impact on other system metrics