1. COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG COMPACT MODEL FOR LONG-CHANNEL SYMMETRIC DOPED DG Antonio Cerdeira 1, Oana Moldovan 2, Benjamín Iñiguez 2 and Magali Estrada 1 1 Sección de Electrónica del Estado Sólido, CINVESTAV, México D.F., cerdeira@cinvestav.mx 2 Departament d´Enginyeria Electrònica, Elèctrica i Automàtica, Universitat Rovira i Virgili,Tarragona, Spaincerdeira@cinvestav.mx TU Munchen MOS-AK/ESSDERC/ESSCIRC Workshop Sept. 14, 2007 TU Munchen MOS-AK/ESSDERC/ESSCIRC Workshop Sept. 14, 2007 Fig. 8 - Gate-source and gate-drain capacitances at drain voltages equal to 0.05 V, 0.5 V and 1 V: from simulation (symbols) and modeled (lines). Si layer doping concentrations is equal to 10 16 cm -3 for constant mobility case equal 400 cm 2 /Vs. Fig 7 - Simulated and modeled I-V characteristics and their derivative around V D = 0 V for Na= 10 17 cm -3 ; V G = 1.5 and t s = 20 nm. a)b) Fig 6 - Simulated and modeled transconductance for Si layer doping concentrations: 10 15 cm -3 and 10 18 cm -3. A) V D = 0.05 V; B) V D = 1 V. Fig 3- Comparison between simulated and modeled linear transfer characteristics for V D = 0.05 V and two Si layer doping concentrations: 10 15 cm -3 and 10 18 cm -3. Fig. 5 - Comparison between simulated and modeled transfer characteristics in saturation for V D = 1 V and two Si layer doping concentrations: 10 15 cm -3 and 10 18 cm -3. Fig 4 - Simulated and modeled output characteristics for V G = 0.5, 1 and 1.5 V for a Si layer doping concentration of 10 15 cm -3 ; 10 17 cm -3 and 10 18 cm -3. Fig 2 - Modeled and numerically calculated potential difference  s-  o as function of gate voltage for different Si layer concentrations and three drain voltages: 0, 0.5 and 1 V. t ox = 2.24 nm and t s = 34 nm. Using the detailed numerical calculation it was found that this magnitude can be expressed by empirical analytical expressions in the analyzed dimension and concentrations range. CHARGE AND CURRENT MODELS Based on the Unified Charge Control Model (UCCM) following expressions were calculated: Normalized to C ox  t movil charge concentration Drain voltage with variable mobility I D : INTRODUCTION The main problem for modeling fully depleted DG devices is that the potential at the surface and the potential at the middle of the silicon layer are related and can not be treated independently one from the other. In addition, the electric field and gate voltage of the device as function of these potentials are expressed by transcendental equations that have no analytical solution. In this paper we present for the first time, an analytical continuous compact model for the current-voltage characteristics, as well as gate-source and gate-drain capacitance in long channel symmetric DG MOSFETs which considers a doped silicon layer and variable mobility. The doping concentration of the silicon layer can vary from 10 14 cm -3 to 3x10 18 cm -3 and gate dielectric and silicon layer thickness, as well as applied voltages can vary in the typically used ranges. In order to validate the expressions for modeling the potential and difference of potentials in symmetric double- gate structures these parameters were also calculated using the numerical procedure proposed by Mallikarjun and the currents were simulated in ATLAS. Surface electric field: Normalized charge at drain in saturation: Effective drain voltage: Saturation voltage: where q s and q d are the normalized charges at source and drain; W- channel width; L- channel length; CONCLUSIONS New compact analytical model for long symmetric double-gate MOSFETs that for the first time, considers a doped silicon layer in a wide range of doping concentrations, between 10 14 and 3x10 18 cm -3, as well as variable mobility with the medium surface electric field. The charge carrier density is calculated using analytical expressions obtained for modeling the surface potential and the difference of potentials at the surface and at the center of the Si doped layer, without the need to solve any transcendental equation or to introduce adjusting parameters. The expressions for modeling the current-voltage and capacitance-voltage were validated using 2D ATLAS simulations. The mobility parameters were extracted from the obtained transfer characteristics. Modeled and simulated transfer characteristics in the linear and saturation regions, output characteristics and gate-drain and gate-source capacitance-voltage characteristics show an excellent agreement between them in all the practical range of gate and drain voltages, silicon layer doping concentrations and equivalent gate dielectric and Si layer thickness confirming the validity of the proposed model. Because of its features, the model can be used for long channel devices or used as core model where the short channel effects can be introduced further. It can be easily implemented in circuit simulators. DG DEVICE STRUCTURE AND POTENTIALS Threshold voltage is calculated by: where Na Silicon layer t s N poly t poly t ox VDVD VGVG VGVG VSVS E 1 = 6300 V/cmP 1 = 0.19  o= 1043 cm 2 /Vs for 10 15 cm -3 E 2 = 1.12x10 6 V/cmP 2 = 1.45 1015 cm 2 /Vs for 10 17 cm -3 793 cm 2 /Vs for 10 15 cm -3 and the surface electric field is defines as: