1. Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide Breakdown Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann 03.09.2009, Natal Institute of Applied Microelectronics and Computer Engineering University of Rostock

2. 2 Outline Motivation and Basics Approaches for reliability enhancements Gate oxide breakdown Redundancy strategies Redundancy on different levels Results Discussion Conclusion / Outlook

3. 3 Motivation – Known approaches Yield enhancements - Layout modifications - Redundancy Soft error resilience - Hardening techniques - Reusing debug resources for redundant flipflops [Mitra] Little effort put into lifetime reliability enhancements Transient failuresPermanent failures Initial failures Failures occuring at runtime Reliability

4. 4 Basics – Gate oxide breakdown Gate oxide breakdown – GOB: Point of time a conducting path between gate and substrate is generated Mainly dependent on: Gate oxide thickness Electrical field at the gate Causes: Sudden extrinsic overvoltage: ESD – Electro-Static Discharge Slow intrinsic destruction over time:TDDB – Time-Dependent Dielectric Breakdown

5. 5 Basics – TDDB Initial traps During operation: generation of overlapping traps Soft breakdown: Creation of a conducting patch Increasing current flow  Heat dissipation  Thermal damage Finally: Hard breakdown Physical mechanism: trap creation R  0

6. 6 Basics – TDDB Finally: Hard breakdown Model by Renovell et al. Follows new research results Gate oxide breakdown harms an affected transistor and its associated cell with a modified delay Whole circuit fails if the timing between the cells is no longer balanced

7. 7 Basics – Scaling issues Scaling increases the gate oxide breakdown problems: Increasing number of transistors within a die Decreasing gate oxide thickness Increase of the electrical field due to non-ideal supply voltage scaling

8. 8 Redundancy strategies Basic multiplier Block duplication Gate duplication Transistor duplication

9. 9 Simulation setup Wallace multiplier Transistor level simulations with HSpice Industrial 65 nm gate library Gate oxide breakdown model of Renovell et al. Implementation of cells with transistors with standard threshold voltage (SVT) and high threshold voltage (HVT)

10. 10 Results – No defects

11. 11 Results – Reliability with defects Simulation results DuplicationMTTF GOB + / - No26.720 % Block21.17- 21 % with HVT-Cells28.42+ 6 % Transistor44.34+ 66 % with HVT-Cells54.71+ 105 % Twin Logic Gates72.52+ 171 % with HVT-Cells80.97+ 203 %

12. Results – Discussion 12 Why is the gate level duplication (Logic Twin Gates) better than transistor duplication? Both implementation only differ in the duplication of the transistor stacks Defect_net 2 is charged to a voltage related to the GOB  Current flow from drain to source of the middle transitor is rather pinched off due to the defect (higher voltage level between lowest two transistors)  Increased fall time of the defect stack  Transistor duplicated stacks are slightly slower due to the cross links

13. 13 Results – Graceful degradation I Increase of the delay with rising defects

14. 14 Results – Graceful degradation I Increase of the delay with rising defects due to increased static power consumption

15. 15 Conclusion Need of design improvements for lifetime reliability Logic Twin Gates promises the most improvements concerning gate oxide breakdown Simple integration of Logic Twin Gates into existing design flows and CAD tools Graceful degradation behavior in the presence of defects

16. 16 Outlook Partial duplication of most vulnerable gates or transistors Usage of benchmark circuits Investigation of the impact of soft breakdowns