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Synchrotron X-Ray Topography for Laser- Drilled Vias Kevin Wang, March 9, 2009.

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Presentation on theme: "Synchrotron X-Ray Topography for Laser- Drilled Vias Kevin Wang, March 9, 2009."— Presentation transcript:

1 Synchrotron X-Ray Topography for Laser- Drilled Vias Kevin Wang, March 9, 2009

2 Through Silicon Via  Via connecting one side of silicon wafer to another  Reduce connection length  Drilling options  Mechanical  Deep Reactive Ion Etching (DRIE)  Laser pulses DRIE Vias, Source: Albany Nanotech

3 Paper  Laser Drilled Through Silicon Vias: Crystal Defect Analysis by Synchrotron X-ray Topography  Landgraf, R., Rieske, R., Danielewsky, A., Wolter, K.  Technische Universtät Dresden, Germany  Synchrotron Source: ANKA (Karlsruhe, Germany)  2.5 GeV,current 80-180 mA: white radiation 2Å  Presented at:  2 nd Electronics System-Integration Technology Conference, Greenwich, UK (2009-09-01)

4 DRIE vs. Laser Drilling DRIE Vias, Source: Lam Research Laser Via, Source: Landgraf Sidewall Scalloping, Source: Aviza Technology

5 Laser Via Fabrication  525μm thick Si wafer (100)  4in. (100mm)  Target via diam: 50 μm

6 Laser Drilling Methods  Single Pulse  Trepanning (cut an annulus)  Percussion (high power pulsing) Conventional drilling patterns, Source: Verhoeven, K.

7 X-ray Diffraction Setup  Section Transmission (15μm slit), Lang Method

8 Results – Strain Imaging ns laser: 540 μm strain zone ps laser: 290 μm strain zone

9 Trend with Laser Pulse Width  Strain affected region:  Distance from via edge to strain edge fs laser: 220 μm strain zone

10 Conclusion  Transmission topography by synchrotron source successfully imaged strain near vias, nondestructively  Strain affected zone decreased with pulse width  Electron-phonon relaxation time in Si, 400fs  Femtosecond lasers should be considered for commercial production  Depth remains to be improved

11 Motivation: Multi-Chip Packages  Wirebonding  Longer paths  Failure due to fatigue, bond lifting  Flipchip bumps  Reduce path length  Still require redistribution layer (RDL)  Thermal cycling failure Flipchip Die, Source: IMEC Wirebonded Die, Source: Aspen Tech.


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