1. Introduction to CMOS VLSI Design Clock Skew-tolerant circuits

2. CMOS VLSI Design 2 Outline  Clock Distribution  Clock Skew  Skew-Tolerant Static Circuits  Traditional Domino Circuits  Skew-Tolerant Domino Circuits

3. CMOS VLSI Design 3 Review Timing Definitions

4. CMOS VLSI Design 4 Clocking  Synchronous systems use a clock to keep operations in sequence –Distinguish this from previous or next –Determine speed at which machine operates  Clock must be distributed to all the sequencing elements –Flip-flops and latches  Also distribute clock to other elements –Domino circuits and memories

5. CMOS VLSI Design 5 Clock Distribution  On a small chip, the clock distribution network is just a wire –And possibly an inverter for clkb  On practical chips, the RC delay of the wire resistance and gate load is very long –Variations in this delay cause clock to get to different elements at different times –This is called clock skew  Most chips use repeaters to buffer the clock and equalize the delay –Reduces but doesn’t eliminate skew

6. CMOS VLSI Design 6 Example  Skew comes from differences in gate and wire delay –With right buffer sizing, clk 1 and clk 2 could ideally arrive at the same time. –But power supply noise changes buffer delays –clk 2 and clk 3 will always see RC skew

7. CMOS VLSI Design 7 Skew Impact  Ideally full cycle is available for work  Skew adds sequencing overhead  Increases hold time too t pd

8. CMOS VLSI Design 8 Cycle Time Trends  Much of CPU performance comes from higher f –f is improving faster than simple process shrinks –Sequencing overhead is bigger part of cycle

9. CMOS VLSI Design 9 Solutions  Reduce clock skew –Careful clock distribution network design –Plenty of metal wiring resources  Analyze clock skew –Only budget actual, not worst case skews –Local vs. global skew budgets  Tolerate clock skew –Choose circuit structures insensitive to skew

10. CMOS VLSI Design 10 Clock Dist. Networks  Ad hoc  Grids  H-tree  Hybrid

11. CMOS VLSI Design 11 Clock Grids  Use grid on two or more levels to carry clock  Make wires wide to reduce RC delay  Ensures low skew between nearby points  But possibly large skew across die

12. CMOS VLSI Design 12 Alpha Clock Grids

13. CMOS VLSI Design 13 H-Trees  Fractal structure –Gets clock arbitrarily close to any point –Matched delay along all paths  Delay variations cause skew  A and B might see big skew

14. CMOS VLSI Design 14 Itanium 2 H-Tree  Four levels of buffering: –Primary driver –Repeater –Second-level clock buffer –Gater  Route around obstructions

15. CMOS VLSI Design 15 Hybrid Networks  Use H-tree to distribute clock to many points  Tie these points together with a grid  Ex: IBM Power4, PowerPC –H-tree drives 16-64 sector buffers –Buffers drive total of 1024 points –All points shorted together with grid

16. CMOS VLSI Design 16 Skew Tolerance  Flip-flops are sensitive to skew because of hard edges –Data launches at latest rising edge of clock –Must setup before earliest next rising edge of clock –Overhead would shrink if we can soften edge  Latches tolerate moderate amounts of skew –Data can arrive anytime latch is transparent

17. CMOS VLSI Design 17 Skew: Latches 2-Phase Latches Pulsed Latches

18. CMOS VLSI Design 18 Dynamic Circuit Review  Static circuits are slow because fat pMOS load input  Dynamic gates use precharge to remove pMOS transistors from the inputs –Precharge:  = 0output forced high –Evaluate:  = 1output may pull low static dynamic

19. CMOS VLSI Design 19 Domino Circuits  Dynamic inputs must monotonically rise during evaluation –Place inverting stage between each dynamic gate –Dynamic / static pair called domino gate  Domino gates can be safely cascaded

20. CMOS VLSI Design 20 Domino Timing  Domino gates are 1.5 – 2x faster than static CMOS –Lower logical effort because of reduced C in  Challenge is to keep precharge off critical path  Look at clocking schemes for precharge and eval –Traditional schemes have severe overhead –Skew-tolerant domino hides this overhead

21. CMOS VLSI Design 21 Traditional Domino Ckts  have high sequencing overhead, hard edge in each half-cycle.  first domino gates does not evaluate until rising edge of the clock, but the results must set up at the latch before falling edge of the clock  If removing the latch, could soften the falling edge and cut the overhead.  The latch serves two functions: –prevent nonmonotonic signals from entering the next domino gate while it evaluates –hold the results of the half-cycle while it precharges and the next half-cycle evaluates.

22. CMOS VLSI Design 22 Traditional Domino Ckts  Hide precharge time by ping-ponging between half-cycles –When clk is high (low), the first half-cycle evaluates (precharges) and the second precharges (evaluates) –Latches hold results during precharge –Overhead of each latch is setup time and D-to-Q propa. delay. assume t pdq is larger, then time for compu. is t pd

23. CMOS VLSI Design 23 Clock Skew  Skew increases sequencing overhead –Evaluate at latest rising edge –Setup at latch by earliest falling edge –Assume skew and setup time > propa. delay t pdq time for computation t pd

24. CMOS VLSI Design 24 Time Borrowing  Logic may not exactly fit half-cycle –No flexibility to borrow time to balance logic between half cycles  Traditional domino sequencing overhead is about 25% of cycle time in fast systems!

25. CMOS VLSI Design 25 Relaxing the Timing  Sequencing overhead caused by hard edges –Data departs dynamic gate on late rising edge –Must setup at latch on early falling edge  Latch functions –Prevent glitches on inputs of domino gates –Holds results during precharge  Is the latch really necessary? –No glitches if inputs come from other domino –Can we hold the results in another way?

26. CMOS VLSI Design 26 Skew-Tolerant Domino  Use overlapping clocks to eliminate latches at phase boundaries. –Second phase evaluates using results of first

27. CMOS VLSI Design 27 Clks nonoverlapping, circuit fails 1.  1 falls, node a precharges high, node b low 2.  2 rises, the input to the first domino gate has fallen, i.e., b is low, node c will never discharge and the circuit loses information.

28. CMOS VLSI Design 28  1 and  2 overlap,  2 rises while b still holds correct value,  2 evaluates using the results of  1 Clks overlapping, circuit works  2 is evaluates, b is low node c is floating

29. CMOS VLSI Design 29 Full Keeper  After second phase evaluates, first phase precharges  Input to second phase falls –Violates monotonicity?  But we no longer need the value  Now the second gate has a floating output –Need full keeper to hold it either high or low

30. CMOS VLSI Design 30 Latch is unnecessary  As long as the clock overlap is long enough that the second phase can evaluate before the first precharges, the latch between phases is unnecessary

31. CMOS VLSI Design 31 Time Borrowing  Overlap can be used to –Tolerate clock skew –Permit time borrowing  No sequencing overhead

32. CMOS VLSI Design 32 Multiple Phases  With more clock phases, each phase overlaps more –Permits more skew tolerance and time borrowing

33. CMOS VLSI Design 33 Clock Generation

34. CMOS VLSI Design 34 Summary  Clock skew effectively increases setup and hold times in systems with hard edges  Managing skew –Reduce: good clock distribution network –Analyze: local vs. global skew –Tolerate: use systems with soft edges  Flip-flops and traditional domino are costly  Latches and skew-tolerant domino perform at full speed even with moderate clock skews.