1. PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS BARIS TASKIN AND IVAN S. KOURTEV UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING

2. Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

3. Introduction Large-scale SOC Time borrowing (cycle stealing) Clock skew scheduling Clock/Timing schedule Minimum clock period

4. Local data path Graph Background

5. Latch Operation Positive level-sensitive

6. Time Borrowing Flip-Flop basedLatch based Higher Operating Frequency! 0.5 T  Data Propagation  T0.5 T  Data Propagation  1.5 T

7. Clock Skew T skew (i,f) = t i - t f Clock signal delay at the initial register Clock signal delay at the final register

8. Clock Skew Scheduling Zero clock skew Non-zero clock skew Higher Operating Frequency! 0.5 T  Data Propagation  T 0.5 T + T SKEW  Data Propagation  T + T SKEW

9. Optimization Problem Flip-flop-based Zero clock skew Latch-based Non-zero clock skew Time borrowing + Clock skew scheduling 0.5 T  Data Propagation  T 0.5 T + T SKEW  Data Propagation  1.5 T + T SKEW

10. Timing Parameters

11. Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

12. Constraints 1. Latching 2. Synchronization 3. Propagation 5. Skew CLOCK SKEW Constant or Variable? 4. Validity

13. Latching Constraints afaf AfAf

14. Synchronization Constraints

15. Max!

16. Propagation Constraints Min ! Max !

17. Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

18. Problem Formulation Timing constraints  NLP problem  Equivalent LP model Modified big M Method

19. Modified big M (MBM) Method min Z  min (Z+Ma) a=max (b,c)  a  ba  ca  ba  c min Z  min (Z-Ma) a=min (b,c)  a  ba  ca  ba  c

20. MBM Method Example Obj: Min Z= 5a+4b s.t. c C1 : c=max(a,b) C2 : a=3 C3 : b=7 NON-LINEAR a bc M c C1a: c  a C1b: cb +1000c LINEAR

21. LP Model Formulation [Synchronization Constraint-I]

22. Implementation and Model Highlights C++ implementation Off-shelf optimizer (CPLEX) Provide stand-alone model –Robust, fast –Sensitivity analysis

23. Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

24. Timing Analysis CIRCUIT TOPOLOGY CLOCKING METHODOLOGY MAX OP. FREQUENCY TIMING SCHEDULE CLOCKING SCHEDULE SENSITIVITY * INPUT OUTPUT

25. Example

26. R1 R3 R2 R4 R5 Circuit C Clock Pin... Additional Constraints t R1 = t R4 = c c:constant Clock signal delays at R 1 and R 4

27. ISCAS’89 Benchmark Results CIRCUIT INFORMATION NON-ZERO SKEW SCHEDULING CONSTRAINED CIRCUIT Circuit No of registers No of data paths TimeI3I3 I4I4 s27330.02s38% s444161130.07s41% s119618200.03s63%23% s38417163628082603s39% s38584145215545321s31% Average---27%24% TIME BORROWING  15% CLOCK SKEW SCHEDULING  14% SIMULTANEOUS  27%

28. Outline Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions

29. Increased performance Time borrowing Clock skew scheduling Complete framework for timing analysis Multi-phase synchronization

30. PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS BARIS TASKIN AND IVAN S. KOURTEV QUESTIONS UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING