1. ECE465 Lecture Notes # 11 Clocking Methodologies Shantanu Dutt UIC Acknowledgement: (1) Most slides prepared by Huan Ren from Prof. Dutt’s Lecture Notes (some modifications made by Prof. Dutt). (2) Some slides extracted from Prof. David Pan’s (UT Austin) slides as indicated.

2. Memory Timing Methodologies Synchronous Sequential Circuits Comb. Logic Clk External I/P External O/P Features Required for Correct Operation –1) All State Transitions take place only with respect to a particular event in the clock (e.g., positive or negative edge, etc. ) A C 11/0 B 00,11/0 01/1 00,01,10/0 01/0 10,00/1 Transition occurs only on positive edge of Clk T OP P,Logic T NS P,Logic (critical path delay In the o/p logic part) (critical path delay In the NS logic part)

3. Timing Methodologies (contd) Features Required for Correct Operation –2) Only one state transition should take place in one clock period. –3) All inputs to all FFs/latches should be correctly available with appropriate setup time (T setup or T su ) and hold time (T hold or T h ) around the triggering edge of the clock. i’th state transition (i+1)’th state transition (i+2)’th state transition (i+3)’th state transition T period =T Clk [could be to the same state] ≥ T setup ≥ T hold Input Clock

4. Clock Routing A path from the clock source to clock sinks (FFs) Different FFs are at different distances from the clock source Clock Source FF From: David Pan, UT Austin This leads to the clock arriving at different FFs at slightly different time. This difference in clock arrival times is called clock skew

5. Timing Methodologies: Clock Skew Problem Real-world problems that can cause the three requirements to be violated –A) Clock Skew: Max(arrival time difference of the “same” clock edge betw all FF pairs). 01 D1D1 FF1 DQ Logic FF2 DQ IN Q1Q1 0  1 D2D2 Q2Q2 0 Clk Clk1Clk2 0010 Current state Correct transition 11 Incorrect transition New value of D2 overwrites old value before Q2 changes This causes an incorrect Q2 change when +ve edge arrives at Clk2 Clk1 Clk2 D1 D2 Q1 Q2 T skew Safe: If blue horse wins race & wins it by a margin of at least T h 2 1 Unsafe: If brown horse wins race 2 1 Values before the clock +ve edge

6. Safe Value of T skew Clk1 Clk2 D1 D2 Q1 ≥T su ≥Th≥Th Typical or min T PLH min T P,Logic T skew ≥Th≥Th 01 D1D1 FF1 DQ Logic FF2 DQ IN Q1Q1 0 D2D2 Q2Q2 0 Clk Clk1 Clk2 Safe if: min (T PLH of FF)+min (T P,Logic between Q 1 & Q 2 )>T skew +T h i.e. if: T skew < min (T PLH )+min (T P,Logic )-T h Similarly for 1 to 0 transition of Q 1 : T PHL comes into play, then safe if : T skew < min (T PHL )+min (T P,Logic )-T h Thus we need: T skew < min (min T PLH, min T PHL )+min (T NS P,Logic ) –T h = min(T P,FF ) + min(T NS P,Logic ) – T h, where T NS P,Logic is the prop. delay of the next state (NS) logic portion of the entire comb. logic in the system. Thus, the safe T skew limit is based on minimum propagation delay of FFs and the NS logic Tskew= max (|difference between clock pulses (rising edges) of clock inputs of any two FFs in the system|)

7. Another problem of clock skew 01 D1D1 FF1 DQ Logic FF2 DQ IN Q1Q1 0 D2D2 Q2Q2 0 Clk1 Clk2 Clk Clk2 Clk1 T skew Less time avail. for logic and FF delays T FF + T logic + T su Clock skew causes another problem: 1.If the clock is not designed taking skew into account, then there will not be enough time to complete the FF-load and comb. logic operations T su time before the next clock edge arrives at Clk2 2.If clock skew is taken into account, as it should be, the clock period T clk will be larger by an amount of T skew, thus making it “unnecessarily” slower T clk

8. Determining Clock Period: Edge Triggered System Comb. Logic FF1 FF2 Clk Clk1 Clk2 Clk Level sens. latch Positive edge trigg. Clk negative edge trigg. Memory of FF bank with delay T P,FF T OP P,Logic Clk1 Clk2 T P,FF T su T P,Logic T skew T Clk T Clk -T skew > max(T P,FF )+ max( TNS P,Logic )+T setup = T P,FF + T NS P,Logic +T setup i.e., we will use the normal convention of using T P,FF to mean max(T P,FF ) T NS P,Logic to mean max(T NS P,Logic ) Also, T Clk -T skew > T P,FF + T OP P,Logic, where T OP P,Logic is the output logic portion of combinational logic. Max(typical T PHL and typical T PLH ) T NS P,Logic

9. Determining the Clock Period (Contd.) If with skew –T Clk > T skew + T P,FF + T NS P,Logic +T setup AND –T Clk > T skew + T P,FF + T OP P,Logic –Thus T Clk > max(T skew + T P,FF + T NS P,Logic +T setup, T skew + T P,FF + T OP P,Logic ) Use 10% buffer for safety –T Clk =1.1max(T skew + T P,FF + T NS P,Logic +T setup, T skew + T P,FF + T OP P,Logic ) T skew = max (|difference between clock pulses (rising edges) of clock inputs of any two FFs in the system|) Clk1 ≥ T P,FF + T NS P,Logic + T setup, AND ≥ T P,FF + T OP P,Logic T Clk

10. Determining the Clock Period of a Datapath w/ a Controller FSM FFs n CLK n Output Logic m2m2 Next State Comb. Logic m1m1 I/Ps (external + from datapath) O/Ps (= Control Signals) Datapath Registers Control logic (muxes, decoders, tri-state buffers, load/enablei/ps) Delay1 = T P,FF + T NS P,Logic +T setup Delay2 = T P,FF + T op P,Logic +max(T control_logic ) FU(s) Subpath delay = T P,FF + T FU(s) + T setup T 1 =max(Delay1, Delay2) A simple technique: Find the approximate greatest common divisor (gsd) of the various subpath delays. Update T 1 =max(Delay1, Delay2, above gsd) T Clk = 1.1T 1 Each subpath w/ delay Di will have cc delay of ceiling(Di/ T Clk ) Ignoring clock skew here for simplicity. Can be added later on after deciding the non-skew clock period by adding 1.1T skew to it.

11. Another Problem in Seq. Circuits: Race Condition A race condition occurs when a FF/latch output changes more than once in a clock cycle (cc). This happens when after the O/P of a latch changes, it feeds back to its input via some logic when the latch is still enabled in the same cc. This cause the O/P to change again. Clk D Q ≥T su 2 changes of state in Q in 1 cc Clk D latch Comb. Logic Other I/Ps D Q

12. Race Condition (contd) Race condition is generally a problem with level sensitive latches. Can be solved using: –a) Edge-triggered FFs. Clk D Q D FF Comb. Logic Other I/Ps Clk D Q –b) Narrow-width clocking. Only 1 O/P change per cc. T Clk TwTw T Clk > T skew + T P,FF + T P,Logic +T setup Tw < min (T P,FF )+min(T P,Logic ) min (min T PLH, min T PHL ) D latch Comb. Logic Other I/Ps D Q Narrow Width Clk

13. Correct State Transition Using Level-Sensitive Latches: No race cond. but potential exists 0010 0/0 0/1 01 1/1 01 1/1 1/0 0/0 Comb. Logic 0 1 0 1 0 1 Transition for the darkened arrow: Clk Comb. Logic 0 1 0 0 1 1 Clk Comb. Logic 0 0 1 0 1 1 Clk 0/1 2 level sens. latches CSNS

14. Race Condition due to unequal path delays for different NS bits: Incorrect State Transition Using Level-Sensitive Latches Required transition for the thick arrow becomes incorrect transition corresponding to the dashed arrow Comb. Logic 0 1 0 1 0 1 Clk Comb. Logic 0 1 0 1 1 1 Clk Comb. Logic 0 1 1 1 1 1 Clk Comb. Logic 1 1 1 0 0 1 Clk Comb. Logic 1 0 0 0 0 1 Clk 2 level-sens. latches fast slow 1/0 0010 0/0 0/1 01 1/1 11 1/1 1/0 0/00/1

15. No Race Condition Using Edge-Triggered FFs 0010 0/0 0/1 01 1/1 01 1/1 1/0 0/0 Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs Comb. Logic 0 1 0 1 0 1 Clk Comb. Logic 0 1 0 1 1 1 Clk Comb. Logic 0 1 0 1 1 1 Clk 0/1 Comb. Logic 0 1 0 0 1 1 Clk Comb. Logic 0 0 1 0 1 1 Clk 2 M-S or edge- triggered FFs fast slow Period Between State Transitions (also clock period)

16. No Race Condition Using 2-phase clocking and MS level sensitive latches Generally, Cost(master-slave (MS) LS latches) < Cost(edge-trigg. FF) Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs 00 100/0 0/1 01 1/1 1/0 0/0 Comb. Logic 0 1 00 1 1 Clk2Clk1 Comb. Logic 0 0 11 0 1 Clk2Clk1 Clk2 Clk1 Comb. Logic 0 1 01 1 1 Clk2Clk1 fast slow Comb. Logic 0 0 01 1 1 Clk2Clk1 fast slow T 2-1 T gap T 1-2 0 1 OR

17. Two-phase clock period determination T gap1 > T skew (to avoid overlap and thus a race condition & this also takes care of the skew problem that reduces that part of clock period available for the delays of the FF + logic + T su ) T 2-1 +  T 1-2 (0 T P,FF +T P,Logic +T su + T skew (1) (Note: Introducing a T gap1 of at least T skew also takes care of the reqmt to allow for T skew in the above sum of the 3 delay components) (1-  )T 1-2 > T P,FF + T su (2) The value of  is really not going to matter, since disappears in  T 1-2 + (1-  )T 1-2 = T 1-2, and on adding (1) and (2) we get: T 2-1 +T 1-2 > 2T P,FF +T P,Logic +2T su (3) T 1-2 = T 2-1 (for symmetry requirements) T gap1 = T gap2 (for symmetry requirements) > T skew  this again takes care also of skew reducing the clock period in the various prop. delays and setup times are incurred. So, finally: T clk = 1.1(T 2-1 + T 1-2 + T gap1 + T gap2 ) = 1.1(2T P,FF +T P,Logic +2T su +2T skew ) [w/ 10% safety gap] Comb. Logic O/PsI/Ps Clk2Clk1 CSNS Clk2 Clk1 T 2-1 T gap1 T 1-2 T Clk T gap2  T 1-2  T 1-2 Note: T gap1 = T gap2 = T skew, takes care of both requirements: a) no overlap in Clk1 and Clk2 due to skew; b) enough clock period T clk to process all delays, where two different arrival times of clk1 (or clk2) at two different master (or slave) latches can differ by T skew (the "usual" problem that we saw for edge-triggered FFs). No extra T skew allowance needed in T clk for the latter issue.

18. Clock Skew Clock skew is the maximum difference in the arrival time of a clock signal at two different components. Clock skew forces designers to use a large time period between clock pulses. This makes the system slower. So, in addition to other objectives, clock skew should be minimized during clock routing. From: David Pan, UT Austin

19. Clock Design Problem What are the main concerns for clock design? Skew –No. 1 concern for clock networks –For increased clock frequency, skew may contribute over 10% of the system cycle time Power –very important, as clock is a major power consumer! –It switches at every clock cycle! Noise –Clock is often a very strong aggressor –May need shielding Delay –Not really important –But slew rate is important (sharp transition) From: David Pan, UT Austin

20. The Clock Routing Problem Given a source and n sinks (FFs). Connect all sinks to the source by an interconnect tree so as to minimize: –Clock Skew = max i,j |t i - t j | –Delay = max i t i –Total wirelength –Noise and coupling effect From: David Pan, UT Austin

21. H-Tree Clock Routing 4 Points 16 Points Tapping Point From: David Pan, UT Austin

22. Method of Means and Medians (MMM) Applicable when the clock terminals are arbitrarily arranged. Follows a strategy very similar to H-Tree. Recursively partition the terminals into two sets of equal size (median). Then, connect the center of mass of the whole circuit to the centers of mass of the two sub-circuits (mean). Clock skew is only minimized heuristically. The resulting tree may not have zero-skew. From: David Pan, UT Austin

23. An Example of MMM centers of mass From: David Pan, UT Austin