1. 1 Digital Design: State Machines Timing Behavior Credits : Slides adapted from: J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006 C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004 R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

2. 2 Timing in clocked sequential circuits The purpose of the clock signal is to synchronize the operation of flip flops and combinational logic in order to prevent timing problems In sequential logic we must examine not only the propagation delays through gates and wires but also the changes relative to clocking events of flip flops.

3. 3 Setup/Hold Time An input to a flip flop can be validly recognized only if: it is stable before the clocking event for a minimum time interval T setup and it is stable after the clocking even for a minimum time interval T hold input clock T su ThTh

4. 4 Setup/Hold Time (cont’d) It is dangerous to allow input signals to change very close to the sampling event If setup or hold time constraints are not satisfied, the input maybe interpreted as a 1 or a 0 or some unrecognizable value between 0 and 1 (metastable value)

5. 5 Timing constraints in clocked sequential circuits Let’s assume that din is applied in a way that satisfies setup and hold for FF1, and let’s examine what will happen at FF2 D Q C combinational logic D Q C din clock dout AB FF1 FF2

6. 6 Timing constraints in clocked sequential circuits (cont’d) clock din A B T su2 D Q C combinational logic D Q din clock dout AB FF1 FF2 C t FF1 tPtP tPtP T clock t FF1 + t P < T clock – T su2 Setup constraint t FF1 t FF1 + t P > T h2 Hold constraint T h2 tPtP

7. 7 Max/Min delays Unfortunately, delays through gates are not constant. Delays change with: Supply Voltage, Temperature, and Manufacturing Process Setup constraint is more difficult to satisfy when delays are max (V , T , P  ) Hold constraint is more difficult to satisfy when delays are min (V , T , P  ) tPtP FF1 FF2 D Q C combinational logic D Q din clock dout AB C t FF1 t FF1 + t P < T clock – T su2 Setup constraint t FF1 + t P > T h2 Hold constraint i +v+v for i constant: if dv decreases, dt must increases

8. 8 Minimum Clock period for a Sequential circuit

9. 9 Clock skew Positive skew makes easier to satisfy setup constraint: t FF1 +t P < T clock –T su2 + t skew t FF1 + t P > T h2 +t skew Positive skew makes more difficult to satisfy hold constraint: tPtP FF1 FF2 D Q C combinational logic D Q din clock dout clock0 B C t FF1 skew t skew clock1 clock0 din = clock clock1 B t FF1 + t P T (0) su t skew T su2 T (0) h T h2 In this example if clock0=clock1 (no skew) setup at FF2 is violated

10. 10 Asynchronous Inputs Synchronous circuits can have asynchronous inputs Even a supposedly synchronous circuit like the D flip flop can have asynchronous inputs such as preset and clear In this case glitches makes asynchronous inputs extremely dangerous and should be avoided Sometimes asynchronous inputs come from signals that must pass from the outside world into the synchronous system In this case it is metastability to become an issue

11. 11 Handling asynchronous inputs The best way to deal with asynchronous signals is to synchronize them to the clocked system

12. 12 Handling asynchronous inputs (cont’d) It is essential for asynchronous inputs to be synchronized at only one place in a system and as soon as possible ► Never allow asynchronous inputs to fan-out to more than one flip-flop ►Synchronize as soon as possible and then treat as synchronous signal DQ DQ Q0 Clock Q1 Async Input Clocked Synchronous System DQ DQ Q0 Clock Q1 Async Input DQ Synchronizer

13. 13 Handling asynchronous inputs (cont’d) Possible problem occurring when synchronizing at more than one place

14. 14 Possible problem with procrastinating synchronization Example of combinational logic hiding the fact that there are two synchronizers. Since different paths through combinational logic will have different delays, the likelihood of an inconsistent result is even greater Handling asynchronous inputs (cont’d)

15. 15 Synchronization Failure What if the asynchronous input to the synchronizer FF changes too close to clock edge the FF may enter a metastable state – neither a logic 0 nor 1 – it may stay in this state an indefinite amount of time this is not likely in practice but has some probability Synchronization failure is said to occur if a system uses a synchronizer output while the output is still in metastable state. The only way to recover from synchronization failure is to reset the entire circuit While the probability of synchronizer failure can be made small, it can never be eliminated as long as there are asynchronous inputs logic 0 logic 1

16. 16 Synchronization Failure (cont’d) There are two ways to get a flip flop out the metastable state : force the flip flop into a valid logic state using input signals that meet the specifications for minimum pulse width, setup and hold time wait “long enough”, so the flip flop comes out of metastability on its own logic 0 logic 1 small, but non-zero probability that the FF output will get stuck in an in-between state logic 0 logic 1 oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state D Q C In FF

17. 17 Metastability Resolution Time (t r ) Maximum time that the output can remain metastable without causing synchronizer (and system) failure

18. 18 Reducing the chance of Synchronizer Failure One way to reduce the probability of synchronizer failure is to use faster flip flops and lengthen the system’s clock period. This gives the synchronizer flip-flop more time to enter a stable state. A second strategy is to place two synchronizers in series. Both flip- flop must be metastable before the synchronization fails (an event with low probability)

19. 19 Analysis of Metastable Timing

20. 20 Analysis of Metastable Timing (cont’d) t r resolution time f frequency of the flip-flop clock  number of asynchronous input changes per second applied to the flip flop T 0 and  constants that depends on the electric characteristics of the flip flop Mean Time Between synchronizer Failures

21. 21 Better synchronizers A way to improve the MTBF lengthen the clock applied to the synchronizer circuit (n  t clk )

22. 22 Better synchronizers (cont’d)

23. 23 Better synchronizers (cont’d) At very high frequency, the feasibility of the multicycle synchronizers is limited by the clock skew