1. Technical Seminar on Timing Issues in Digital Circuits
National Institute of Science & Technology
Presented by
Madhumita Mandal EE
Under the Guidance of
Mr. M. Suresh
[1]

2. INTRODUCTION Timing Issues in Digital Circuits
All sequential circuits must have a well-defined ordering of the switching events
This can be enforced using the synchronous system approach
Impact of Clock Skew and Clock Jitter
Introduction of techniques to cope with both
The overview of the asynchronous design or the self timed logic
National Institute of Science & Technology
[2]
Madhumita Mandal (EE )

3. DIGITAL TIMING ANALYSIS TOOLS
Timing Issues in Digital Circuits
DIGITAL TIMING ANALYSIS TOOLS
An Analysis Tool must be accurate in proving or disproving correctness
Different tools are-
Logic simulators-model digital circuit operation in software
Static Timing Verifiers-constructs directed graph from the circuit
Hand Analysis and other Computer Methods
National Institute of Science & Technology
Madhumita Mandal (EE )
[3]

4. TIMING CLASSIFICATION OF DIGITAL SYSTEMS
Timing Issues in Digital Circuits
TIMING CLASSIFICATION OF DIGITAL SYSTEMS
In Digital systems, signals can be classified based on their relation with a local clock
Synchronous Interconnect-It has exact frequency as local clock
National Institute of Science & Technology
Madhumita Mandal (EE )
[4]

5. TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Timing Issues in Digital Circuits
TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Mesochronous interconnect:
A mesochronous signal- has the same frequency as the local clock, as well as an unknown phase offset with respect to that clock
In Figure,signal D1 is synchronous with respect to clkA
National Institute of Science & Technology
Madhumita Mandal (EE )
[5]

6. TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Timing Issues in Digital Circuits
TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Plesiochronous
Interconnect:
Frequency is slightly different than the local clock
This causes phase difference to drift in time
C1 is plesiochronous with respect to C2
National Institute of Science & Technology
Madhumita Mandal (EE )
[6]

7. TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Timing Issues in Digital Circuits
TIMING CLASSIFICATION OF DIGITAL SYSTEMS(contd.)
Asynchronous Interconnect:
Asynchronous signals can transition arbitrarily at any time
They are not slaved to any local clock
Advantageous because computations are performed at the native speed of the logic
National Institute of Science & Technology
National Institute of Science & Technology
[7]
Madhumita Mandal (EE )

8. SYNCHRONOUS DESIGN Timing Issues in Digital Circuits
All systems designed today use a periodic synchronization signal or clock
Clock Constraints are:
T>tc-q+tlogic+tsu &
Thold<tc-q,cd+tlogic,cd
the clock signal can have both spatial and temporal variations
National Institute of Science & Technology
National Institute of Science & Technology
[8]
Madhumita Mandal (EE )

9. CLOCK SKEW Timing Issues in Digital Circuits
Definition:The spatial variation in arrival time of a clock transition on an integrated circuit
The rising clock edge is delayed by a positive  at the second register
National Institute of Science & Technology
Madhumita Mandal (EE )
[9]

10. CLOCK SKEW (contd.) Timing Issues in Digital Circuits
Negative clock skew:
In this case (>0), performance is improved, but, it makes thold harder to meet
Here, the clock and data flow in opposite directions
National Institute of Science & Technology
Madhumita Mandal (EE )
[10]

11. CLOCK JITTER Timing Issues in Digital Circuits
Clock jitter refers to the temporal variation of the clock period at a given point on the chip
The total time available to complete the operation is
Tclk - 2tjitter  tc-q + tlogic + tsu Or
T  tc-q+ tlogic + tsu + 2tjitter
National Institute of Science & Technology
Madhumita Mandal (EE )
[11]

12. SOURCES OF SKEW AND JITTER
Timing Issues in Digital Circuits
SOURCES OF SKEW AND JITTER
The sources of clock uncertainty are:
systematic and random
Systematic errors are nominally identical from chip to chip and are predictable
Random errors are due to manufacturing variations
National Institute of Science & Technology
Madhumita Mandal (EE )
[12]

13. Timing Issues in Digital Circuits
ECL LOGIC TECNOLOGIES
ECL Logic Technologies provide for Reducing System Clock Skew .
Advantages are:
Skew Reductions
Low Impedance Line Driving
Differential Interconnect
Using ECL with positive power supplies
National Institute of Science & Technology
Madhumita Mandal (EE )
[13]

14. CLOCK DISTRIBUTION NETWORKS
Timing Issues in Digital Circuits
CLOCK DISTRIBUTION NETWORKS
A clock network that minimizes both clock skew and jitter
An H-tree configuration is particularly useful for regular array networks
The most common type of clock distribution scheme is the H- tree network
National Institute of Science & Technology
Madhumita Mandal (EE )
[14]

15. SELF-TIMED LOGIC Timing Issues in Digital Circuits
A reliable technique to avoid the problems of synchronous design is the self-timed approach
The computation of a logic block is initiated by asserting a start signal
The automatic shutdown of blocks that are not in use can result in power savings
National Institute of Science & Technology
Madhumita Mandal (EE )
[15]

16. CONCLUSION Timing Issues in Digital Circuits
Clock skew and jitter substantially impact the functionality and performance of a system
Important parameters are the clocking scheme used and the nature of the clock generation and distribution network.
Alternative timing approaches, such as self-timed design, are becoming attractive for dealing with clock distribution problems
National Institute of Science & Technology
Madhumita Mandal (EE )
[16]