1. MICAS Department of Electrical Engineering (ESAT) AID–EMC: Low Emission Digital Circuit Design Status of the “Digital EMC project” Junfeng Zhou Wim Dehaene

2. MICAS Department of Electrical Engineering (ESAT) Logic styles under investigation Logic style 1. Standard CMOS logic 2. Pseudo NMOS logic 3. CSL (CMOS Current Steering Logic) 4. MCML (MOS Current Mode Logic--differential version of CSL)

3. MICAS Department of Electrical Engineering (ESAT) Why CSL ? Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Current Steering Logic

4. MICAS Department of Electrical Engineering (ESAT) CSL – Static Characteristic Design Parameter: R= Vdd=2.5v I=20uA C load =20fF

5. MICAS Department of Electrical Engineering (ESAT) CSL – Noise Margin Vdd=2.5v I=20uA C load =20fF 300mV R >4

6. MICAS Department of Electrical Engineering (ESAT) CSL – Dynamic Characteristic Vdd=2.5v I=20uA C load =20fF

7. MICAS Department of Electrical Engineering (ESAT) The Effect of Decoupling Capacitance There is a Trade off ! Cd Vdd=3.3v I=10uA R=6 C load =20fF di/dt 1p1p 10p,100p,1n,10n

8. MICAS Department of Electrical Engineering (ESAT) Comparison of 16-bit RCA, CSL vs. SCMOS Note: V DD =1.5v The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. Solution: power consumption management power down, sleep transistors, switching activity improvement …

9. MICAS Department of Electrical Engineering (ESAT) Spectrum Analysis of di/dt 10 5 6 7 8 9 70 80 90 100 110 120 130 140 150 Power Spectral Analysis of the CMOS 16-bit RCA Frequency (Hz) Power 30db decrease

10. MICAS Department of Electrical Engineering (ESAT) Variants of CMOS inverter Variant 1Variant 2

11. MICAS Department of Electrical Engineering (ESAT) The effect of decoupling capacitance Time domain 10fF 100fF 1pF 10pF100pF1nF

12. MICAS Department of Electrical Engineering (ESAT) The effect of decoupling capacitance Frequency domain Bit rate=100MHz

13. MICAS Department of Electrical Engineering (ESAT) CSL D-type Flip-Flop master slave

14. MICAS Department of Electrical Engineering (ESAT) Clock=50MHz Comparison of D-FF Spectrum, CSL vs. SCMOS 38dB reduction

15. MICAS Department of Electrical Engineering (ESAT) Intentional clock skew Principle Circuit under Simulation

16. MICAS Department of Electrical Engineering (ESAT) The effect of clock skew on the reduction of di/dt No skew 120ps skew Time domain

17. MICAS Department of Electrical Engineering (ESAT) The effect of clock skew on the reduction of di/dt Frequency domain

18. MICAS Department of Electrical Engineering (ESAT) Spread Spectrum Clocking ---SSC 1. Frequency modulating(FM) the clock signal with a unique modulating waveform. 2. The total power of the switching noise remains the same. Figure 1. Frequency domain representation at a harmonic of a clock signal with and without SSC Figure 2. Time domain representation of the modulated clock signal Hardin, K.B. Fessler, J.T. Bush, D.R., ” Spread spectrum clock generation for the reduction of radiated emissions”, IEEE International Symposium on Electromagnetic Compatibility, 1994, pp 227-231

19. MICAS Department of Electrical Engineering (ESAT) Digital Pseudo Random Modulation-PRM Figure 3 Circuit implementation of PRM Figure 4 Timing diagram of PRM

20. MICAS Department of Electrical Engineering (ESAT) Test circuit F nominal = 40MHz F modulation = 1GHz N=3,M=8 Figure 5 Test circuit under simulation

21. MICAS Department of Electrical Engineering (ESAT) Comparison of Spectrum Spread Spectrum Clock Regular Clock 12dB reduction Figure 6 Spectrum from 300MHz to 800MHz Zoom in promising