1. A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization Time-interleaved ADC array –High sampling rate, low power –Channel mismatch errors Offset, gain, linearity and skew Approaches –Correlation, statistics, and Chopping Slow convergence, involved analog path, ad-hoc solutions –Equalization Fast convergence, digital post-processing, systematic solution

2. Equalization-Based Conversion Architecture Channel mismatch errors automatically eliminated w/ equalization !

3. Performance Summary fs = 600 MS/s, Ain = 0.9 FS Process (µm) fs (MS/s) SFDR (dB) SNDR (dB) Power (mW) FOM (pJ) Ours0.13060065.247.323.60.21 ISSCC 060.1306004333.15.30.22 ISSCC 080.06525048281.20.24 VLSI 080.0658005847.8300.28