1. www.hypertransport.org 1 Extreme Interconnect Performance Extended Applicability May 16, 2006 Introducing HyperTransport TM 3.0 David Rich President HyperTransport Consortium Brian Holden Vice President Chair Technical Working Group HyperTransport Consortium Mario Cavalli General Manager HyperTransport Consortium

2. www.hypertransport.org 2 TechOnLine Webcast May 16, 2006 … … … HyperTransport Consortium Owns and Licenses HyperTransport Technology Founding Members Founded: 2001 Mission: The standardization of a low latency, high-bandwidth interconnect serving a broad range of next-generation high-performance electronic industry applications Joined by Tens of World Technology Leaders From … … to HyperTransport Consortium

3. www.hypertransport.org 3 TechOnLine Webcast May 16, 2006 HyperTransport TM Processor-to-Processor, Processor-to-I/O, Processor to High-Performance Peripherals Interconnect Best End-User Performance CPU Native Lowest Latency Highest Bandwidth Broad System Scalability 2-Bit to 32-Bit Links Asymmetric Links Support Easy Multiprocessor Scalability Minimum Silicon Deployment Less Control Logic Less Power Consumption Industry answer to: HyperTransport Profile HTX TM HTX TM Connectivity Lowest Latency Direct Connect Between CPU (s and Peripherals via Standardized Direct HyperTransport Links 16-Bit or 8-Bit Wide 6.4GB/s Bandwidth Eliminates Performance Bottlenecks of Compute-Intensive Peripherals and Co-Processing Subsystems

4. www.hypertransport.org 4 TechOnLine Webcast May 16, 2006 Core Differentiators HyperTransport TM (*) HyperTransport Profile (cont.)

5. www.hypertransport.org 5 TechOnLine Webcast May 16, 2006 Adopted by Technology Leaders in Widest Range of Market Segments HyperTransport Profile (cont.)

6. www.hypertransport.org 6 TechOnLine Webcast May 16, 2006 Market Statistics HyperTransport Profile (cont.) Summary Forecast of Worldwide HyperTransport Systems – 2003-2009 (Units in Thousands) Source: In-Stat 8/05

7. www.hypertransport.org 7 TechOnLine Webcast May 16, 2006 Interconnect Landscape High Performance Interconnect Evolution HyperTransport Delivers Widest Application Latitude

8. www.hypertransport.org 8 TechOnLine Webcast May 16, 2006 Server Clustering Standard Interconnects Weave Off-the-Shelf Servers into Powerful Scalable Clusters Server Clustering Makes HPC a Commodity! Major Industry Trends Major Industry Trends Bank on HyperTransport Core Compute and Storage Functionality No Legacy I/O Control Subsystem Clustered via High-Bandwidth Low Latency Multi-Gb/s Interconnect Cost Saving Times “n” Factor Reduced Power Consumption Increased Reliability Localized Legacy I/O Processing Performance/Cost-Optimized Data-Center Servers

9. www.hypertransport.org 9 TechOnLine Webcast May 16, 2006 High-Performance Co-Processing Functions Compute-Intensive Applications Served by Standard CPU Platforms Tightly Coupled With Application-Specific Co-Processing Subsystems Commodity-Level Systems Minimize TCO Co-Processing Approach Tailors Performance to Application at Optimized System Cost Target Markets Low Latency Clustering Security Monitoring Network Protocol Analysis Algorithm Acceleration Storage Management Encryption/Decryption Others Major Industry Trends Bank on HyperTransport HTX Connector DDR Memory Others DDR Memory Vacant Opteron Socket

10. www.hypertransport.org 10 TechOnLine Webcast May 16, 2006 200M HT Ports Shipped Technology Milestones 2001 HT 1.0HT 2.0 2002 2004 2003 2005 HT 1.1HTX Connectivity 30M HT Ports Shipped 2006 HyperTransport Evolution HT 3.0

11. www.hypertransport.org 11 TechOnLine Webcast May 16, 2006 Why HyperTransport TM 3.0? Need for Lowest Latency and Highest Bandwidth Server Clusters Parallel Processing Co-Processing Design Flexibility Direct Cross-System Processor-to-Processor Interconnects Simplified Interconnect Protocol Intelligent System Configuration Escalating Power Consumption Concerns Lower Total Cost of Ownership Fewer Technologies Inside and Outside the Box Higher Reliability Support for Next Generation Processors Higher Throughput More Interconnect Links HyperTransport Evolution (cont.)

12. www.hypertransport.org 12 TechOnLine Webcast May 16, 2006 HyperTransport 3.0 State-of-the-Art Specifications 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz Clock Support 41.6 GB/s Aggregate Bandwidth 20.8 GB/s (166.4 Gb/s) per Link DC Operating Mode Enhancements AC Operating Mode (Optional) Supports Applications Requiring Greater Signal Interconnect Distance Cables Backplanes Larger Physical Systems Chassis-to-Chassis Interconnects DC/AC Auto-Configuration Link-Splitting/Un-Ganging Mode (Optional) Auto-configuration of Bi-Mode 2x8 or 1x16 Links Hot Plugging Backplanes Applications Power Management Enhancements (Optional) Support Dynamic Link Frequency and Width 100% Backward Compatibility Auto-Configuration at Boot-Up with Minimum Spec Common Denominator Selection State-of-the-Art Specifications Same Features as HT 2.0 Plus:

13. www.hypertransport.org 13 TechOnLine Webcast May 16, 2006 Doubling Performance - Again (*) HT 3.0 20.8 GB/s (Aggregate) HT 2.0 11.2 GB/s (Aggregate) Twice HyperTransport 2.0’s 16-bit Throughput With No Increase in System Design Complexity and Real Estate Penalty/Cost State-of-the-Art Specifications (cont.) 1.4 GHz 1.8 GHz 2.0 GHz 2.2 GHz 2.4 GHz 2.6 GHz Clock (*) HyperTransport 2.0 Doubled HyperTransport 1.x Performance in February 2004

14. www.hypertransport.org 14 TechOnLine Webcast May 16, 2006 DC Operational Mode Enhancements State-of-the-Art Specifications (cont.) Transmitter Enhanced Training Pattern Tolerates Multi-Bit Skew Added Scrambling Enables Rx Phase Alignment Retained Clock Forwarding Scheme on Dedicated Lane(s) Maximized System Performance Predictability – Scales with System Architecture Receiver Enabled Use of Rx Equalization Support for Multi-Bit Skew Through Clock-Based Rx Phase Alignment 100% Backwards Compatible Runs in HyperTransport 1.x and 2.0 Mode when New Features Not Enabled

15. www.hypertransport.org 15 TechOnLine Webcast May 16, 2006 AC Operating Mode - Optional State-of-the-Art Specifications (cont.) Significantly Extends HyperTransport Usability Latitude Inf Supports Backplane, Board-to-Board, Chassis-to-Chassis Implementations AC-Coupling Capacitors 8B/10B for DC Balance Tx Equalization Lower Bandwidth, Higher Latency than DC Mode Enabled when Needed – Best of Both Worlds Transmit with Pre- and Post-Cursor De-Emphasis

16. www.hypertransport.org 16 TechOnLine Webcast May 16, 2006 DC/AC Auto-Configuration State-of-the-Art Specifications (cont.) Between Existing Low-Latency DC Mode and New Long-Reach AC Mode Circuitry Detects Presence of Coupling Capacitors Auto-Switches to AC Mode Allows System Vendors to Connect the Same HyperTransport Device in DC Mode for Short Runs and AC Mode for Long Runs DC Coupling AC Coupling

17. www.hypertransport.org 17 TechOnLine Webcast May 16, 2006 Link-Splitting Mode - Optional (Un-Ganging) State-of-the-Art Specifications (cont.) Auto-Configuration of Bi-Mode 2x8 or 1x16 Link Width More HyperTransport Ports Useful in Topologies Such As Symmetric Multi-Processing (SMP) Required by Vendors Interested in Dual-Mode Interfaces 2x 8-Bit Links1x 16-Bit Link

18. www.hypertransport.org 18 TechOnLine Webcast May 16, 2006 Link-Splitting + AC Mode Powerful Multi-processor Expansion Capability State-of-the-Art Specifications (cont.) 8-Bit DC HyperTransport Links16-Bit DC HyperTransport Links HTX Connector I/O CPU To other CPU subsystems To other CPU subsystems Chassis 1 HTX Connector I/O CPU To other CPU subsystems To other CPU subsystems Chassis n 16-Bit AC HyperTransport Links Max 3.0 clock speed with cables up to 1m in length

19. www.hypertransport.org 19 TechOnLine Webcast May 16, 2006 Hot Plugging State-of-the-Art Specifications (cont.) Ability to Add /Remove Devices from HyperTransport Fabric Without Disrupting Other Operations Defined Link Termination Methods Transaction Termination Behaviors Sync Flood Isolation Link Training Times Parameter Configuration Mechanisms Important in High-Availability Applications, Server and Storage Markets

20. www.hypertransport.org 20 TechOnLine Webcast May 16, 2006 Power Management Enhancements - Optional State-of-the-Art Specifications (cont.) Dynamic Link Frequency and Width Allows Implementation to Dynamically Change Frequency and Width of a Link Rapid Pause-Change-Start Support Implements in Hardware Answer to Increasing Importance of Power Consumption

21. www.hypertransport.org 21 TechOnLine Webcast May 16, 2006 Meeting Present and Future Application Requirements Aggregate Bandwidth 8.0 GB/s 41.6 GB/s 520% Link Width 16-bit 32-bit 100% Clock Speed 1.0 GHz 2.6 GHz 162% Operational Mode DC DC or AC Distance Max Use Max Capable At Present 3.0 Specs Headroom HyperTransport TM State-of-the-Art Specifications (cont.)

22. www.hypertransport.org 22 TechOnLine Webcast May 16, 2006 HyperTransport 3.0 Already In Demand Where from Here HPC System Manufacturers Consider HT 3.0 Highly Strategic for Next-Generation Product Roadmap Vastly Improved Processor-to-Processor Interconnect Flexibility and Performance In-Chassis and Chassis-to-Chassis Optimized Parallel Processing Operations SMP Architectural and Cost Optimization Server and High-Performance Workstation Companies Regard HyperTransport 3.0 as Painless Path to Performance Doubling of 16-Bit Link Designs without Added System Design and PCB Real Estate Complexity

23. www.hypertransport.org 23 TechOnLine Webcast May 16, 2006 Questions and Answers Introducing HyperTransport 3.0 All product trademarks included in this presentation are the property of their respective owners For more information about HyperTransport technology please visit the “Technology” page on our Consortium’s web portal at www.hypertransport.org or call us at 925-968-0220 www.hypertransport.org