1. Assume array size is 256 (mult: 4ns, add: 2ns)*
A[i] B[i]
Option-1 +
temp
sum
Path delay 6ns
Cycle time: 6ns
Clock rate: 166.6MHz
166.6x106 MAC/sec

2. Assume array size is 256 (mult: 4ns, add: 2ns)*
A[i] B[i] *
A[i] B[i] *
A[i+1] B[i+1] *
A[i+2] B[i+2] *
A[i+3] B[i+3]
Option-2 +
temp
sum + + +
Path delay : 10ns
Cycle time: 10ns
Clock rate: 100MHz
400x106 MAC/sec
Path delay 6ns
Cycle time: 6ns
Clock rate: 166.6MHz
166.6x106 MAC/sec +
temp
sum

3. Assume array size is 256 (mult: 4ns, add: 2ns)*
A[0] B[0] *
A[1] B[1] *
A[2] B[2] *
A[3] B[3] *
A[254] B[254] *
A[255] B[255]
Option-3
Adder tree ( 8 levels) + + +
Path delay : 4 + 8*2 + 2 = 22ns
Cycle time: 22ns
Clock rate: 45.5MHz
11.36x109 MAC/sec +
temp
sum

4. Assume array size is 256 (mult: 4ns, add: 2ns)*
A[i] B[i] *
A[i] B[i] *
A[i+1] B[i+1] *
A[i+2] B[i+2] *
A[i+3] B[i+3]
Option-4 +
temp
sum + + +
Critical path delay : 4ns
Cycle time: 4ns
Clock rate: 250MHz
109 MAC/sec
Path delay 6ns
Cycle time: 6ns
Clock rate: 166.6MHz
166.6x106 MAC/sec +
temp
sum

5. Exercise: Serial vs. Pipelined Assume array size is N (add: 2ns)+
A[i] B[i] +
A[i+1] B[i+1] +
A[i+2] B[i+2] +
A[i+3] B[i+3] +
A[i] B[i] +
A[i+1] B[i+1] +
A[i+2] B[i+2] +
A[i+3] B[i+3] + + + + + +
N=48
N=100,000
temp
temp
Serial:
12 cycles
cycle time: 6ns
Pipelined:
= 14 cycles
cycle time: 2ns
~2.57x
Serial:
25,000 cycles
cycle time: 6ns
Pipelined:
= cycles
cycle time: 2ns
~2.99x

6. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Flip-flop samples D at clock edge and D must be stable when sampled
Similar to a photograph, D must be stable around clock edge
If not, metastability can occur
Setup time: tsetup = time before clock edge data must be stable (i.e. not changing)
Hold time: thold = time after clock edge data must be stable
Aperture time: ta = time around clock edge data must be stable (ta = tsetup + thold)

7. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Propagation delay: tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing)
Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)

8. Sequential Logic Design Non-Ideal Flip-Flop Behavior
The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements

9. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Depends on the maximum delay from register R1 through combinational logic to R2
The input to register R2 must be stable at least tsetup before clock edge
Tc ≥

10. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Depends on the maximum delay from register R1 through combinational logic to R2
The input to register R2 must be stable at least tsetup before clock edge
Tc ≥ tpcq + tpd + tsetup
tpd ≤

11. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Depends on the maximum delay from register R1 through combinational logic to R2
The input to register R2 must be stable at least tsetup before clock edge
Tc ≥ tpcq + tpd + tsetup
tpd ≤ Tc – (tpcq + tsetup)

12. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tpd =
tcd =
Setup time constraint:
Tc ≥
fc =

13. Sequential Logic Design Non-Ideal Flip-Flop Behavior
Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
tsetup = 60 ps
thold = 70 ps
tpd = 35 ps
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
Setup time constraint:
Tc ≥ ( ) ps = 215 ps
fc = 1/Tc = 4.65 GHz

14. Clock Skew The clock doesn’t arrive at all registers at same time
Skew: difference between two clock edges
Perform worst case analysis to guarantee dynamic discipline is not violated for any register – many registers in a system!

15. Clock Skew
In the worst case, CLK2 is earlier than CLK1
Tc ≥

16. Clock Skew Tc ≥ tpcq + tpd + tsetup + tskew tpd ≤
In the worst case, CLK2 is earlier than CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
tpd ≤

17. Clock Skew Tc ≥ tpcq + tpd + tsetup + tskew
In the worst case, CLK2 is earlier than CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
tpd ≤ Tc – (tpcq + tsetup + tskew)

18. Sequential Logic Design Metastability
Violating setup/hold time can lead to bad situation known as metastable state
Metastable state: Any flip-flop state other than stable 1 or 0
Eventually settles to one or other, but we don’t know which
For internal circuits, we can make sure observe setup time
But what if input comes from external (asynchronous) source, e.g., button press?
Partial solution
Insert synchronizer flip-flop for asynchronous input
Special flip-flop with very small setup/hold time
Doesn’t completely prevent metastability a

19. Sequential Logic Design Metastability
One flip-flop doesn’t completely solve problem
How about adding more synchronizer flip-flops?
Helps, but just decreases probability of metastability
So how solve completely?
Can’t! May be unsettling to new designers. But we just can’t guarantee a design that won’t ever be metastable. We can just minimize the mean time between failure (MTBF) -- a number often given along with a circuit
Probability of flip-flop being metastable is…
very
very
very
incredibly l o w
low
low l o w ai
synchronizers

20. Exercise
Circuit shown below computes the 4-input AND function using 2-input AND gates. Each 2-input AND gate has a propagation delay of 100ns and a contamination delay of 55ns. Each flip flop has a setup time of 30ns, a hold time of 20ns, a clock-to-Q maximum delay of 70ns, and a clock-to-Q minimum delay of 50ns.
a) If there is no clock skew, what is the maximum operating frequency of the circuit?
b) How much clock skew can the circuit tolerate if it must operate a 2MHz

21. Exercise-2
Determine the critical path and clock frequency of the following design provided. Assume
the setup time of a D flip-flop is 10 ns.
assume the delay is estimated as 1 ns times the number of gate inputs.
mux delay = 5 ns
adder delay = 20 ns A B
4-bit Adder
clr ld 1 -1 4
Cnt Reg
Cnt
cnt_clr
cnt_ld
sel
State Reg n1 n0 s1 s0 up en