1. Computer Organization

2. This module surveys the physical resources of a computer system. –Basic components CPUMemoryBus I/O devices –CPU structure Registers Processing units –Instruction cycle

3. CPU and the Memory The Central Processing Unit (CPU) –responsible for instruction execution –determines how the memory is to be modified –contains a few data container called registers The Main Memory –large collection of data containers –each is labeled with a positive integer called its address For each instruction, the CPU fetches input data from registers or memory, then writes output to a register or memory location

4. Instruction Types Arithmetic and logical instructions apply a function to input data to produce output –Addition, logical AND, negation Control instructions test or compare values of variables and make decisions about what instruction is going to be executed next –The only output is a possible change in the register that keeps track of the address of the next instruction This special register is often called the program counter (PC)

5. Fetch-Decode-Execute Cycle The CPU is endlessly looping through these steps –Actual steps will vary from processor to processor MIPS R2000 steps 1. instruction fetch & PC update 2. instruction decode & operand load 3. operation execution (control instructions update PC) 4. memory access 5. register update

6. Basic Architecture Processor (CPU) Main Memory –volatile I/O devices –secondary memory –communications –terminals System interconnection –a bus is used to exchange data and control information CPUMemory System Bus Disk Controller Network Controller Serial Device Controller

7. Interconnection: the bus Conceptually, a collection of parallel wires, each of which is dedicated to carrying one of –data –address –control (of access to the bus) Only one component can “write” to a particular wire of the bus at a time data address control

8. Device Controllers Devices are not connected directly to the system bus Each device has a device controller between it and the system bus One controller may have multiple devices For example: SCSI devices, IDE devices, USB devices CPUMemory System Bus Disk Controller Network Controller Serial Device Controller

9. I/O Devices Each device has a buffer which mediates data transfer. Transfer between memory and devices is limited by the size and speed of the data bus. For example, though a disk reads data to its buffer one block at a time, transfer to memory is one word at a time. CPUMemory System Bus Device Controller buffer

10. Memory Can be viewed as a linear array of data values –Indexed by non-negative integers: addresses –Memory is usually byte addressable each byte has its own unique address –The word-size (width of the data bus) of a system is often more than 1 byte In the MIPS architecture, the word-size is 4 bytes 2 31 –1 0

11. Central Processing Unit Arithmetic logic unit (ALU) –performs arithmetic and logic operations Control unit –reads and decodes instructions –initiates execution of instruction by proper component Registers –some have special purpose CPU ALUControl PC IR PSW AR CP DP SP CL DL v0 a0s0s1s2s3

12. CPU Design CPU design defines what the computer’s instruction do and how they are specified (the instruction set) The instruction set determine the computer’s capabilities. –All computers should be able to implement any logical function on a finite number of bits. Such instruction sets are said to be complete –Not all complete designs are equal! Execution time may vary… A computer’s machine language is determined by its manufacturer The assembly language is also formally defined by the manufacturer

13. 0$zero1$at 2$v0 3$v1 4$a0 … 7$a3 8$t0 … 15$t7 16$s0 23…$s7 24$t8 25$t9 26$k0 27$k1 28$gp 29$sp 30$fp 31$ra MIPS ALU Registers  Value is always zero  Used by the assembler for address  Return values from functions  Pass parameters to functions `  Caller saved register  Callee saved registers  More caller saved registers  Used by the kernel (operating system)  Global pointer  Stack pointer  Frame pointer  Return address (used by JAL instruction)