1. What is the most effective approach to design for low power? Panel Session 16:00-17:00, July 9, 2007 DESIGN AND VALIDATION CHALLENGES OF MULTI-CORE SYSTEMS IN NANOSCALE SILICON INTEL’S ANNUAL SYMPOSIUM ON VLSI CAD AND VALIDATION TECHNION

2. Panelists Yoad Yagil (Intel) George Stamoulis (U Thessaly) Zvi Boiangou (Cadence) Ken Stevens (U Utah) Eyal Ronen (Intel) David Blaawu (U Michigan)

3. What is the most effective approach to design for low power? What do VLSI designers do? –Strategy A: Seek improvements within their own domain of expertise.

4. What is the most effective approach to design for low power? What do VLSI designers do? –Strategy A: Seek improvements within their own domain of expertise – Strategy B: Blame others and tell them to fix the problem Logic designers blame architects Architects blame logic designers Both blame library designers Everyone blame process developers!

5. What is the most effective approach to design for low power? What do VLSI designers do? –Strategy A: Seek improvements within their own domain of expertise – Strategy B: Blame others and tell them to fix the problem Logic designers blame architects Architects blame logic designers Both blame library designers Everyone blame process developers! Can we think about another strategy? What is the most effective approach?

6. Questions for the panelists Who is really to blame for wasting power? What power saving can be gained within each domain separately? What are the most effective approaches? What can be gained by working across domains?