1. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 1© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Nils Büscher, Lennard Lender FIR Filter Design Results of Phase 2 Selected Topics in VLSI Design

2. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 2© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Content Coefficient Modifications Carry-Select-Adder Frequency Response Metric Observations / Conclusion

3. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 3© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Coefficient Modifications 6-bit coefficients with 2 non-zero bits Partial product: Shifted and/or inverted input value 2 zero coefficients Adder tree removed

4. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 4© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Carry-Select-Adder Dedicated FPGA carry-logic is only instanciated by using „+“ or „-“ in VHDL Last sum bit of a 4-bit RCA is a function of 8 arguments  chain of two LUTs Adder: Used in last stage Operands: 24-bit sum vector 24-bit carry vector 3 pipeline stages

5. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 5© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Frequency Response

6. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 6© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Metric (Backannotated) ReferencePhase 1Phase 2 Frequency~ 83 MHz~ 200 MHz709,723 MHz* LUTs16993095437 D-FFs288905753 # Stages125 Static Power242 mW244 mW Dyn. Power53 mW253 mW276 mW Metric [MHz 4 /W]1.61 * 10 8 3.22 * 10 9 4.88 * 10 11 *Max. Total Setup Delay: 1.171 ns (~854 MHz) Min. Clock Pulse Width: 1.408 ns (~710 MHz) generated with Vivado default synthesis and implementation settings

7. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 7© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Observations / Conclusion CSDs are very efficient, less adder stages needed Reducing input data width Leads to much smaller design Mathematical incorrect result FPGA: think in LUTs <> ASIC: think in gatters e. g. a 4:2 compressor is approx. as fast as a 3:2 adder

8. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 8© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Thank you for your attention!

9. Institute of Applied Microelectronics and Computer Engineering 20.05.2015 9© 2014 UNIVERSITY OF ROSTOCK | College of Computer Science and Electrical Engineering Overall Layout Same structure as last time (direct form II) Accumulated sum of inverted input vectors Reduction of logic depth