1. Lecture 5: Decision and Control CS 2011 Fall 2014, Dr. Rozier

2. LOGISTICS

3. Logistics 9/16 – Today 9/18 – Continued Instructions 9/23 – Continued Instructions 9/25 – Exam Review 9/30 – Midterm I

4. LADIES AND TIGERS

5. The Lady and the Tiger Two doors containing either Ladies or Tigers

6. The Lady and the Tiger Once again, you’ll have to tell Ladies from Tigers A new twist is being added. – In Room I, if a lady is in the room, the sign will be true. If a tiger is in the room, the sign will be false. – In Room II, the situation is the opposite!

7. The Lady and the Tiger Q1 Room I Both rooms contain ladies. Room II Both rooms contain ladies.

8. The Lady and the Tiger Q1 Room IRoom II

9. The Lady and the Tiger Q2 Room I At least one room contains a lady Room II The other room contains a lady

10. The Lady and the Tiger Q2 Room IRoom II

11. The Lady and the Tiger Q3 Room I It makes no difference which room you pick. Room II The other room contains a lady.

12. The Lady and the Tiger Q3 Room IRoom II

13. CURRENT PROGRAM STATUS REGISTER

14. CPSR The Current Program Status Register – Special register that holds information on the side effects of instructions. – Condition code flags N – Negative result from the ALU Z – Zero result from the ALU C – ALU operation Carried out V – ALU operation oVerflowed

15. CPSR Operand 1 – 32 bits Operand 2 – 32 bits Result – 32 bits

16. CPSR FlagLogical InstArith Inst N = 1No meaningBit 31 of the result has been set. Indicates a negative number for signed operations Z = 1Result bits are all zero Result of the operation was zero C = 1After shift operation a ‘1’ was left in the carry Result was greater than 32 bits V = 1No meaningResult was greater than 31 bits, possible corruption of sign bit

17. CPSR The CPSR bits are set by: Compare/Test instructions: – The only effect of a comparison is to UPDATE THE CONDITIONS FLAGS. CMP : op1 – op2 CMN: op1 + op2 TST: op1 AND op2 TEQ: op1 EOR op2

18. CPSR The CPSR bits are set by: Data processing operations do not normally effect CPSR! – Can be caused to effect them by adding the S bit of the instruction.

19. CPSR The CPSR bits are set by: Data processing operations and CPSR – Add the “S” suffix to set the “S” bit. – ADDS – SUBS – ANDS

20. Conditional Execution The NZCV flags form the basis for conditional execution in the ARM, one of its most powerful features. – Most architectures must use “branch” or “jump” instructions. – The ARM can enable or disable individual instructions based on the CPSR.

21. Conditional Execution

22. EQ – enable this instruction if the results of the last CMP or “S” instruction indicate equality: Example: CMP r0, r1 ADDEQ r0, r0, r1

23. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 What does this mean to the processor?

24. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 r0 - r1, and set NZCV flags – EQ is the conditional execution suffix for r0 == r1. – NE is the conditional execution suffix for r0 != r1. – HI is the unsigned conditional execution suffix for r0 > r1 – LO is the unsigned conditional execution suffix for r0 < r1 In groups, what are the values of NZCV that enable these conditionals?

25. Conditional Execution To understand conditional execution, let’s think in terms of CMP. – CMP r0, r1 r0 - r1, and set NZCV flags – HS is the conditional execution suffix for r0 >= r1. – LS is the conditional execution suffix for r0 <= r1. In groups, what are the values of NZCV that enable these conditionals?

26. Conditional Execution How would you build GT, GE and LT, LE (the signed equivalents)?

27. Conditional Execution CodeSuffixMeaningCodeSuffixMeaning 0000EQZ = 11001LSC = 0 || Z = 1 0001NEZ = 01010GE(N=1 && V=1) || (N=0 && V=0) 0010HS/CSC = 11011LT(N=1 && V=0) || (N=0 && V=1) 0011LO/CCC = 01100GTZ=0 && ((N=1 && V=1) || (N=0 && V=0)) 0100MIN = 11101LEZ=1 || ((N=1 && V=0) || (N=0 && V=1)) 0101PLN = 01110ALAlways 0110VSV = 11111NVReserved/deprec ated 0111VCV = 0 1000HIC = 1 && Z = 0

28. BRANCHING

29. Branching Conditional execution isn’t the only tool in our belt.

30. Branching Branches allow us to transfer control of the program to a new address. – b ( ) – bl ( ) b start bl start

31. Branching Basic branches do not operate on registers. Typically we branch to an indicated LABEL, example: MAIN: b END END: b MAIN

32. Branching Branches are calculated by the assembler relative to the current address. – Allows branching +/- 32 Mbytes Branch stores the target address in the Program Counter Branch and link also stores the next address in the link register.

33. Branch (b) Branch, possibly conditionally, to a new address. beq subroutine @ If Z=1, branch Good practice to use bal instead of b.

34. Branch with link (bl) Branch, possibly conditionally, to a new address. – Before the branch is complete, store the PC in the LR. – Allows easy return from the branch. bleq subroutine @ If Z=1, branch, saving the PC

35. Branch with link (bl) How do we get back once we’ve saved the PC? mov pc, lr Moves the contents of the link register to the program counter.

36. Implementing If Statements C code: if (i == j) f = g+h; else f = g - h; ARM code cmp r0, r1 @ Set flags via r0-r1 and discard beq Else add r2, r3, r4 @ r2 = r3 + r4 bal Exit Else: sub r2, r3, r4 @ r2 = r3 + r4 Exit:

37. Implementing Loop Statements C code: while (i < j) i += 1; ARM code Loop: cmp r0, r1 bge Exit add r0, r0, #1 bal Loop Exit: i < j? i=i+1 i<j Exit i>=j

38. Basic Blocks A basic block is a sequence of instructions with – No embedded branches (except at end) – No branch targets (except at beginning) A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks

39. For next time Continue discussion of Chapter 2 on Thursday.