1. Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December 2003 (sareibi@uoguelph.ca, zyang@uoguelph.ca) ICM 2003, Cairo

2. Outline Congestion Optimization Motivation Experimental Results Summary & Conclusions Background Introduction ICM 2003, Cairo

3. Introduction The interconnect has become a critical determiner of circuit performance in the deep sub-micron regime. Circuit placement is starting to play an important role in today’s high performance chip designs. In addition to wire length optimization, the issue of reducing excessive congestion in local regions such that the router can finish the routing successfully is becoming another important problem. ICM 2003, Cairo

4. VLSI Design Physical Design Partitioning Routing Placement 4 Specification Architectural design Circuit design Physical design Test/Fabrication Logic design

5. Layout Styles Semi Custom Full Custom Standard Cell Cell-BasedArray- Based Macro CellGate ArrayFPGA Layout Style 5

6. Standard Cell Layout Style Feature:  Row based layout  Standard cells  Routing channel Advantages:  High productivity  More efficient space  Well-suited for automated design Standard cell Routing Channel I/O Pads Feedthrough 6

7. Circuit Layout - Partitioning 8 Partition circuit into several sub-circuits.  Minimize the number of connections between the components.  Make the size of each Objectives component within prescribed ranges Task

8. Circuit Layout - Placement 2 1 4 3 8 6 5 7 In8 In7 In6 In5 In4 In3 In2 In1 Out1 8 152 364 7 In8 In5 In2 In1In3 In 4 In6 In7 Out1  Minimize the total estimated wire length of all the nets.  Minimize the interconnect congestion. 8

9. Circuit Layout – Global Routing Minimize the total wire length and critical path delay. 10 Objectives

10. Circuit Layout Typical Objectives  Minimize the chip area  Minimize the interconnect delay L D W H O R L E T O L H OLE WLORD  Determine the location of modules.  Connect the modules inside the boundary of a VLSI chip. 10

11. Why Is Placement Important?  The first phase in the VLSI design that determines the physical layout of a chip. - The quality of the attainable routing is highly determined by the placement. 11 - Circuit Placement becomes very critical in today’s high performance VLSI design.  The circuit delay, power dissipation and area are dominated by the interconnections. 1.0um0.5um0.25um 1.0 0.1 Minimum Feature Size Delay (ns0 Gate delay Interconnect delay

12. Placement Techniques Placement Algorithms Constructive Placement Iterative Improvemen t Partitioning Placement Numerical Optimizatio n Cluster Growth Technique Simulated Annealin g Force-directed Placement Genetic Placement 12

13. Traditional Placement Approach Initial (global) Placement by Constructive Algorithms Initial (global) Placement by Constructive Algorithms Improve (detailed) Placement by Iterative Algorithms Improve (detailed) Placement by Iterative Algorithms Valid Coordinates for each cell  Produce a good initial placement in reasonable time  Produce a good final placement Circuit Generated From Logical Description 13

14. Multi-Level Clustering 1.Bottom-up procedure (clustering) 2. Top-down procedure (de-clustering) initial placement iterative improvement a simple interchange heuristic a high quality solution de-cluster clusters formed from cells in previous level clusterde-cluster cluster Level n Level 1 Level 0 (Flat)........ 14

15. Traditional Methods: Drawbacks May lead to routing detours around the regions ( i.e. larger routed wire length). May create an unroutable placement( i.e leads to replacement and repartitioning).unroutable Congestion reduction in placement stage would be more effective. ICM 2003, Cairo

16. Congestion ICM 2003, Cairo Global Bin Global Bin Edge Routing demand = 3 Assume routing supply is 1, overflow = 3 - 1 = 2. Overflow on each edge = Routing Demand - Routing Supply 0 (otherwise) Total Overflow = overflow all edges 

17. Congestion Reduction Techniques Congestion Reduction Integrated Technique Post-processing Technique Partitioning Based Placement Simulated Annealing Quadratic Placment Congestion Reduction During Placment ICM 2003, Cairo

18. Congestion Optimization ICM 2003, Cairo Initial Placement Congestion Reduction Iterative Improvement Valid Coordinates for each cell Module Description & Netlist Routing Estimation Congested Region Expanding Congested Region Identification Congestion Reduction

19. Routing Estimation  Bounding Box Routing Estimation. bin(0,0) bin(0,2) bin(2,0) Net K Total Horizontal Routing Demand of net K :2 For each yellow bin, the Horizontal Routing Demand of net K is:1/3  Based on the probability of having a wire within a global bin covered by the bounding box of net K: ICM 2003, Cairo

20. Congestion Cost Function Cost = Routing Demand +( Overflow) 2  Wire lengthOverflow Horizontal Routing Demand: 2 Vertical Routing Demand: 2 Total Bounding Box Based Wire length: 4 ICM 2003, Cairo

21. Identifying Congested Regions A global bin is congested if one of its four global edges is congested. A maximum number of congested bins in one congested region is set to prevent forming too large congested regions. ICM 2003, Cairo Bin(i,j)Neighborhood bins Congested Reg_3 Congested Reg_1 Congested Reg_2

22. Congested Region Expansion For a single congested region, the larger the expansion area is, the better the optimization result can be obtained. However, the expansions of multiple congested regions may lead to new congested regions. ICM 2003, Cairo Original Congested Region Expansion Area

23. Test Circuits CircuitcellsPadsNetsPinsRows Fract125241478766 Prim175281904552616 Struct1888641920547121 Ind122718142478851316 Prim2290710730291840728 Bio64179757422694746 Ind2121424951341912555572 Avq.s2185464221248260180 Avq.l2511464253848275186 LargeSmallMedium ICM 2003, Cairo

24. Experimental Results ICM 2003, Cairo  Test Circuit Statistics (for flat approach) CircuitcellsNetsGrids#c/binV/H Cap Fract1251476x92.36/6 Prim175290416x212.211/10 Struct1888192021x322.88/7 Ind12271247815x542.819/7 Prim22907302928x492.116/13 Bio6417574246x602.311/10 Ind2121421341972x762.217/20 Ind3150592194054x1112.527/20 Avq.s218542212480x1142.412/10 Avq.l251142538486x1202.212/10

25. Congestion Reduction (at flat level) ICM 2003, Cairo Average Congestion imp: 51% Average Wire length Increase: 3% Average CPU Time Increase: 30%

26. Congestion Reduction (at level-3) ICM 2003, Cairo

27. Results Analysis Incorporating a post processing technique into the hierarchical placement may not be an effective way to reduce the congestion due to the interplay between the wire length placement algorithm and congestion reduction technique. The wire length minimization should be performed on clustering levels, while the congestion optimization should be only turned on at the flat level. ICM 2003, Cairo

28. Congestion Reduction (after hierarchy) ICM 2003, Cairo Average Congestion imp:37% Average Wire length Increase: 3%

29. Conclusions and Summary A post-processing congestion reduction technique is implemented and incorporated into the flat and hierarchical placement. A post-processing technique can reduce the congestion of flat placement largely by 51% on average with a slight increase of wire length. For hierarchical congestion-driven placement, it seems to be more beneficial to incorporate the congestion reduction phase at the flat level rather than within the levels of hierarchy. The congestion improvement achieved by performing congestion optimization at the flat level is 37% on average. ICM 2003, Cairo

31. Congestion Driven Placement D EFGH ACB A EFGH DCB (channel capacities:2) UnroutableUnroutable Layout Shorter Wire length Channel Density: 3 (track: 3) Longer Wire length Channel Density: 2 (track: 2) ICM 2003, Cairo